research-article

Towards reliable 5Gbps wave-pipelined and 3Gbps surfing interconnect in 65nm FPGAs

Authors:

Guy G.F. Lemieux,

Mark R. GreenstreetAuthors Info & Claims

FPGA '09: Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays

Pages 43 - 52

https://doi.org/10.1145/1508128.1508136

Published: 22 February 2009 Publication History

Abstract

FPGA user clocks are slow enough that only a fraction of the interconnect's bandwidth is actually used. There may be an opportunity to use throughput-oriented interconnect to decrease routing congestion and wire area using on-chip serial signaling, especially for datapath designs which operate on words instead of bits. To do so, these links must operate reliably at very high bit rates. We compare wave pipelining and surfing source-synchronous schemes in the presence of power supply and crosstalk noise. In particular, supply noise is a critical modeling challenge; better models are needed for FPGA power grids. Our results show that wave pipelining can operate at rates as high as 5Gbps for short links, but it is very sensitive to noise in longer links and must run much slower to be reliable. In contrast, surfing achieves a stable operating bit rate of 3Gbps and is relatively insensitive to noise.

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Cited By

Segal CDalakoti AMiller MBrewer FTaskin BHo T(2016)Connectivity Effects on Energy and Area for Neuromorphic System with High Speed Asynchronous Pulse Mode LinksProceedings of the 18th System Level Interconnect Prediction Workshop10.1145/2947357.2947365(1-7)Online publication date: 4-Jun-2016
https://dl.acm.org/doi/10.1145/2947357.2947365
Miller MMagazzu GBrewer F(2016)5 Gbps Radiation-Hardened Low-Power Pulse Serial LinkIEEE Transactions on Nuclear Science10.1109/TNS.2015.250755163:1(203-212)Online publication date: Feb-2016
https://doi.org/10.1109/TNS.2015.2507551
Hui LKapre N(2015)Enhancing Speedups for FPGA Accelerated SPICE through Frequency Scaling and Precision ReductionProceedings of the 2015 IEEE International Parallel and Distributed Processing Symposium Workshop10.1109/IPDPSW.2015.100(163-169)Online publication date: 25-May-2015
https://dl.acm.org/doi/10.1109/IPDPSW.2015.100
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Index Terms

Towards reliable 5Gbps wave-pipelined and 3Gbps surfing interconnect in 65nm FPGAs
1. Hardware
  1. Robustness
  2. Very large scale integration design
    1. VLSI system specification and constraints

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Published In

cover image ACM Conferences

FPGA '09: Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays

February 2009

302 pages

ISBN:9781605584102

DOI:10.1145/1508128

General Chair:
Paul Chow
University of Toronto, Canada
,
Program Chair:
Peter Cheung
Imperial College London, UK

Copyright © 2009 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Publication History

Published: 22 February 2009

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FPGA '09

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FPGA '09: ACM/SIGDA International Symposium on Field Programmable Gate Arrays

February 22 - 24, 2009

California, Monterey, USA

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Overall Acceptance Rate 125 of 627 submissions, 20%

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Cited By

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https://dl.acm.org/doi/10.1145/2947357.2947365
Miller MMagazzu GBrewer F(2016)5 Gbps Radiation-Hardened Low-Power Pulse Serial LinkIEEE Transactions on Nuclear Science10.1109/TNS.2015.250755163:1(203-212)Online publication date: Feb-2016
https://doi.org/10.1109/TNS.2015.2507551
Hui LKapre N(2015)Enhancing Speedups for FPGA Accelerated SPICE through Frequency Scaling and Precision ReductionProceedings of the 2015 IEEE International Parallel and Distributed Processing Symposium Workshop10.1109/IPDPSW.2015.100(163-169)Online publication date: 25-May-2015
https://dl.acm.org/doi/10.1109/IPDPSW.2015.100
Murray KBetz VBetz VConstantinides G(2014)Quantifying the cost and benefit of latency insensitive communication on FPGAsProceedings of the 2014 ACM/SIGDA international symposium on Field-programmable gate arrays10.1145/2554688.2554786(223-232)Online publication date: 26-Feb-2014
https://dl.acm.org/doi/10.1145/2554688.2554786
Miller MBrewer FMagazzu G(2014)5GB/s radiation hard low power point to point serial link2014 19th IEEE-NPSS Real Time Conference10.1109/RTC.2014.7097493(1-4)Online publication date: May-2014
https://doi.org/10.1109/RTC.2014.7097493
Belghadr AJahanian A(2014)Metro-on-FPGAIntegration, the VLSI Journal10.1016/j.vlsi.2013.07.00247:1(96-104)Online publication date: 1-Jan-2014
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Madheswaran MMenakadevi T(2013)An Improved Direct Digital Synthesizer Using Hybrid Wave Pipelining and CORDIC algorithm for Software Defined RadioCircuits, Systems, and Signal Processing10.1007/s00034-012-9495-x32:3(1219-1238)Online publication date: 1-Jun-2013
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Meher MChing Chuen Jong Chip-Hong Chang (2012)An Area and Energy Efficient Inner-Product Processor for Serial-Link Bus ArchitectureIEEE Transactions on Circuits and Systems I: Regular Papers10.1109/TCSI.2012.222047159:12(2945-2955)Online publication date: Dec-2012
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Kapre NDeHon A(2012)${\rm SPICE}^2$IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2011.217319931:1(9-22)Online publication date: 1-Jan-2012
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Meher MChing Chuen Jong Chip-Hong Chang (2011)A High Bit Rate Serial-Serial Multiplier With On-the-Fly Accumulation by Asynchronous CountersIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2010.206037419:10(1733-1745)Online publication date: 1-Oct-2011
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