High-performance asynchronous pipeline using embedded delay element

In this paper, a novel N-bit single-rail pipeline denoted as Embedded Delay Pipeline (EDP) is proposed. It consists of N-Embedded Delay Elements (EDEs) which act both as control elements and as matched delay elements which produce two different delays during precharge and evaluation periods. EDP needs to satisfy only one timing constraint and requires less wiring load between the handshaking stages which leads to less energy consumption per operation. The proposed pipeline is well suited for very fine-grain or gate level pipelining. To evaluate the performance of the EDP, 8-bit Ripple Carry Adder (RCA) is implemented individually using the EDP, Single-rail Look ahead pipelines (LP_sr2/2 and LP_sr2/1) and Single-rail Dynamic elastic pipeline (S-DELP) in UMC-90 nm technology and studied through simulation. From this study, it is found that EDP can operate at a maximum frequency of 2.38 GHz and has 9.6%, 7.5% and 18.5% higher throughput than that of LP_sr2/2, LP_sr2/1 and S-DELP respectively. The energy per operation required for 8-bit RCA using EDP is 127.80 fJ which is 22.50%, 24.15% and 60.13% lower compared to that required for LP_sr2/2, LP_sr2/1 and S-DELP respectively.