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High-throughput and low-power DSP using clocked-CMOS circuitry

Authors:

Manjit Borah,

Robert Michael Owens,

Mary Jane IrwinAuthors Info & Claims

ISLPED '95: Proceedings of the 1995 international symposium on Low power design

Pages 139 - 144

https://doi.org/10.1145/224081.224106

Published: 23 April 1995 Publication History

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Cited By

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Singh MNowick S(2007)MOUSETRAPIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2007.89873215:6(684-698)Online publication date: 1-Jun-2007
https://dl.acm.org/doi/10.1109/TVLSI.2007.898732
Doboli A(2001)Integrated hardware-software co-synthesis for design of embedded systems under power and latency constraintsProceedings of the conference on Design, automation and test in Europe10.5555/367072.367828(612-619)Online publication date: 13-Mar-2001
https://dl.acm.org/doi/10.5555/367072.367828
Singh MNowick S(2001)MOUSETRAP: ultra-high-speed transition-signaling asynchronous pipelinesProceedings 2001 IEEE International Conference on Computer Design: VLSI in Computers and Processors. ICCD 200110.1109/ICCD.2001.954997(9-17)Online publication date: 2001
https://doi.org/10.1109/ICCD.2001.954997
Show More Cited By

Index Terms

High-throughput and low-power DSP using clocked-CMOS circuitry
1. Hardware
  1. Integrated circuits
    1. Interconnect
      1. Input / output circuits
    2. Logic circuits
  2. Very large scale integration design
    1. Application-specific VLSI designs

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Published In

ISLPED '95: Proceedings of the 1995 international symposium on Low power design

April 1995

233 pages

ISBN:0897917448

DOI:10.1145/224081

Chairmen:
Massoud Pedram
USC, Los Angeles, CA
,
Robert Brodersen
UCB, Berkeley, CA
,
Kurt Keutzer
Synopsys, Mountain View, CA

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 23 April 1995

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Article

Conference

LPD95

Sponsor:

SIGDA
IEEE-CAS

LPD95: Low Power Design Symposium

April 23 - 26, 1995

California, Dana Point, USA

Acceptance Rates

Overall Acceptance Rate 398 of 1,159 submissions, 34%

Upcoming Conference

ISLPED '24

Sponsor:
sigda

ACM/IEEE International Symposium on Low Power Electronics and Design

August 5 - 7, 2024

Newport Beach , CA , USA

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Cited By

View all

Singh MNowick S(2007)MOUSETRAPIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2007.89873215:6(684-698)Online publication date: 1-Jun-2007
https://dl.acm.org/doi/10.1109/TVLSI.2007.898732
Doboli A(2001)Integrated hardware-software co-synthesis for design of embedded systems under power and latency constraintsProceedings of the conference on Design, automation and test in Europe10.5555/367072.367828(612-619)Online publication date: 13-Mar-2001
https://dl.acm.org/doi/10.5555/367072.367828
Singh MNowick S(2001)MOUSETRAP: ultra-high-speed transition-signaling asynchronous pipelinesProceedings 2001 IEEE International Conference on Computer Design: VLSI in Computers and Processors. ICCD 200110.1109/ICCD.2001.954997(9-17)Online publication date: 2001
https://doi.org/10.1109/ICCD.2001.954997
Doboli A(2001)Integrated hardware-software co-synthesis and high-level synthesis for design of embedded systems under power and latency constraintsProceedings Design, Automation and Test in Europe. Conference and Exhibition 200110.1109/DATE.2001.915087(612-619)Online publication date: 2001
https://doi.org/10.1109/DATE.2001.915087
de Angel ESwartzlander E(2001)Switching activity in parallel multipliersConference Record of Thirty-Fifth Asilomar Conference on Signals, Systems and Computers (Cat.No.01CH37256)10.1109/ACSSC.2001.987045(857-860 vol.1)Online publication date: 2001
https://doi.org/10.1109/ACSSC.2001.987045
Nagendra COwens RIrwin M(1996)Design tradeoffs in high speed multipliers and FIR filtersProceedings of the 9th International Conference on VLSI Design: VLSI in Mobile Communication10.5555/525699.834747Online publication date: 3-Jan-1996
https://dl.acm.org/doi/10.5555/525699.834747
de Angel ESwartzlander E(1996)Low power parallel multipliersVLSI Signal Processing, IX10.1109/VLSISP.1996.558332(199-208)Online publication date: 1996
https://doi.org/10.1109/VLSISP.1996.558332
Lemonds C(1996)A high throughput 16 by 16 bit multiplier for DSP cores1996 IEEE International Symposium on Circuits and Systems. Circuits and Systems Connecting the World. ISCAS 9610.1109/ISCAS.1996.541750(477-480)Online publication date: 1996
https://doi.org/10.1109/ISCAS.1996.541750
De Angel ESwartzlander E(1996)Survey of low power techniques for VLSI design1996 Proceedings. Eighth Annual IEEE International Conference on Innovative Systems in Silicon10.1109/ICISS.1996.552423(159-169)Online publication date: 1996
https://doi.org/10.1109/ICISS.1996.552423
Nagendra CIrwin M(1996)Design tradeoffs in CMOS FIR filtersProceedings of the Acoustics, Speech, and Signal Processing, 1996. on Conference Proceedings., 1996 IEEE International Conference - Volume 0610.1109/ICASSP.1996.550572(3260-3263)Online publication date: 7-May-1996
https://dl.acm.org/doi/10.1109/ICASSP.1996.550572
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