Article

Two-Phase Asynchronous Wave-Pipelines and Their Application to a 2D-DCT

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S. A. HussAuthors Info & Claims

ASYNC '99: Proceedings of the 5th International Symposium on Advanced Research in Asynchronous Circuits and Systems

Page 219

Published: 19 April 1999 Publication History

Abstract

The two-phase asynchronous wave-pipeline design style presented in this paper is targeted at VLSI systems operating at Giga rates where it is rather difficult and costly to maintain the synchronous paradigm. Its distinguishing properties are the use of a request signal only, simple latches and the inelastic wave-pipelined operation. The asynchronous wave-pipeline is found to have less overhead and to be more robust than the synchronous one. The same basic structure is suitable for both data and control. Buildings blocks of a distributed arithmetic-based 2D-DCT are shown. Simulations of circuits to be fabricated on a 0.6um CMOS process show throughput rates as high as 800$\,$MHz for the 2D-DCT.

References

[1]

D. W. Dobberpuhl, "Circuits and Technology for Digital's StrongARM¿ and ALPHA Microprocessors," Proceedings 17th Conference on Advanced Research in VLSI, pp. 2-11, Sep. 1997.

Digital Library

[2]

S. Anderson, J. Earle, R. Goldschmidt, and D. Powers, "The IBM system/360 model 91 floating point execution unit," IBM Journal of Research and Development, vol. 11, pp. 34-53, Jan. 1967.

Digital Library

[3]

L. W. Cotten, "Maximum-rate pipeline systems," AFIPS Proceedings Spring Joint Computer Conference, vol. 34, Montvale, NJ: AFIPS Press, pp. 581-586, May 1969.

Digital Library

[4]

R. Heald et al., "64-KByte Sum-Addressed-Memory Cache with 1.6-ns Cycle and 2.6-ns Latency," IEEE Journal of Solid-State Circuits, vol. 33, no. 11, pp. 1682-1689, Nov. 1998.

[5]

W. P. Burleson, M. Ciesielski, F. Klass, and W. Liu, "Wave-Pipelining: A Tutorial and Research Survey," IEEE Transactions on VLSI, vol. 6, no. 3, pp. 464-474, Sep. 1998.

Digital Library

[6]

C. Gray, W. Liu, and R. Cavin, Wave Pipelining: Theory and CMOS Implementation, Kluwer, 1994.

[7]

K. J. Nowka, High-Performance CMOS System Design Using Wave Pipelining, PhD Thesis, Computer Systems Laboratory, Stanford University, Aug. 1995.

Digital Library

[8]

O. Hauck and S. A. Huss, "Asynchronous Wave Pipelines for High Throughput Datapaths," Proceedings 5th IEEE International Conference on Electronics, Circuits and Systems, pp. 283-286, Sep. 1998.

[9]

O. Hauck, M. Garg, and S. A. Huss, "Efficient and Safe Asynchronous Wave-Pipeline Architectures for Datapath and Control Unit Applications," Proceedings Ninth Great Lakes Symposium on VLSI, March 1999.

Digital Library

[10]

D. Kearney and N. Bergmann, "Performance Evaluation of Asynchronous Logic Pipelines with Data Dependant Processing Delays," Second Working Conf. on Asynchronous Design Methodologies, pp. 4-13, May 1995.

Digital Library

[11]

O. Hauck, H. Sauerwein, and S. A. Huss, "Asynchronous VLSI Architectures for Huffman Codecs," Proceedings IEEE ISCAS, June 1998.

[12]

K.-Y. Khoo and A. N. Willson, Jr., "Single-Transistor Transparent-Latch Clocking," Proceedings 16th Conference on Advanced Research in VLSI, pp. 331-341, March 1995.

Digital Library

[13]

M.-T. Sun, T.-C. Chen, and A. M. Gottlieb, "VLSI Implementation of a 16×16 Discrete Cosine Transform," IEEE Transactions on Circuits and Systems, vol. 36, no. 4, pp. 610-617, April 1989.

[14]

R. Smith, K. Fant, D. Parker, R. Stephani, and C.-Y. Wang, "An Asynchronous 2-D Discrete Cosine Transform Chip," Proceedings ASYNC'98, pp. 224-233, April 1998.

Digital Library

[15]

D. Johnson, V. Akella, and B. Stott, "Micropipelined Asynchronous Discrete Cosine Transform (DCT/IDCT) Processor," IEEE Transactions on VLSI, vol. 6, no. 4, pp. 731-740, Dec. 1998.

Digital Library

Cited By

Singh MNowick S(2007)MOUSETRAPIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2007.89873215:6(684-698)Online publication date: 1-Jun-2007
https://dl.acm.org/doi/10.1109/TVLSI.2007.898732
Feng TJin BWang JPark NKim YLombardi FVassiliadis SGaudiot JPiuri V(2004)Fault tolerant clockless wave pipeline designProceedings of the 1st conference on Computing frontiers10.1145/977091.977142(350-356)Online publication date: 14-Apr-2004
https://dl.acm.org/doi/10.1145/977091.977142

Two-Phase Asynchronous Wave-Pipelines and Their Application to a 2D-DCT
1. Hardware

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cover image Guide Proceedings

ASYNC '99: Proceedings of the 5th International Symposium on Advanced Research in Asynchronous Circuits and Systems

April 1999

ISBN:0769500315

Copyright © Copyright (c) 1998 Institute of Electrical and Electronics Engineers, Inc. All rights reserved.

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IEEE Computer Society

United States

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Published: 19 April 1999

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Cited By

Singh MNowick S(2007)MOUSETRAPIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2007.89873215:6(684-698)Online publication date: 1-Jun-2007
https://dl.acm.org/doi/10.1109/TVLSI.2007.898732
Feng TJin BWang JPark NKim YLombardi FVassiliadis SGaudiot JPiuri V(2004)Fault tolerant clockless wave pipeline designProceedings of the 1st conference on Computing frontiers10.1145/977091.977142(350-356)Online publication date: 14-Apr-2004
https://dl.acm.org/doi/10.1145/977091.977142

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