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- research-articleMay 2022
Stealth ECC: a data-width aware adaptive ECC scheme for DRAM error resilience
DATE '22: Proceedings of the 2022 Conference & Exhibition on Design, Automation & Test in EuropePages 382–387As DRAM process technology scales down and DRAM density continues to grow, DRAM errors have become a primary concern in modern data centers. Typically, data centers have adopted memory systems with a single error correction double error detection (...
- research-articleAugust 2017
Word- and Partition-Level Write Variation Reduction for Improving Non-Volatile Cache Lifetime
ACM Transactions on Design Automation of Electronic Systems (TODAES), Volume 23, Issue 1Article No.: 4, Pages 1–18https://doi.org/10.1145/3084690Non-volatile memory technologies are among the most promising technologies for implementing the main memories and caches in future microprocessors and replacing the traditional DRAM and SRAM technologies. However, one of the most challenging design ...
- research-articleSeptember 2015
An Energy-Efficient Last-Level Cache Architecture for Process Variation-Tolerant 3D Microprocessors
IEEE Transactions on Computers (ITCO), Volume 64, Issue 9Pages 2460–2475https://doi.org/10.1109/TC.2014.2378291As process technologies evolves, tackling process variation problems is becoming more challenging in 3D (i.e., die-stacked) microprocessors. Process variation adversely affects performance, power, and reliability of the 3D microprocessors, which in turn ...
- research-articleJune 2012
Exploiting narrow-width values for process variation-tolerant 3-D microprocessors
DAC '12: Proceedings of the 49th Annual Design Automation ConferencePages 1197–1206https://doi.org/10.1145/2228360.2228581Process variation is a challenging problem in 3D microprocessors, since it adversely affects performance, power, and reliability of 3D microprocessors, which in turn results in yield losses. In this paper, we propose a novel architectural scheme that ...
- research-articleJuly 2009
On the exploitation of narrow-width values for improving register file reliability
IEEE Transactions on Very Large Scale Integration (VLSI) Systems (ITVL), Volume 17, Issue 7Pages 953–963https://doi.org/10.1109/TVLSI.2009.2017441Protecting the register value and its data buses is crucial to reliable computing in high-performance microprocessors due to the increasing susceptibility of CMOS circuitry to soft errors induced by high-energy particle strikes. Since the register file ...
