research-article

Word- and Partition-Level Write Variation Reduction for Improving Non-Volatile Cache Lifetime

Authors:

Guangshan Duan,

Qianhao DongAuthors Info & Claims

ACM Transactions on Design Automation of Electronic Systems (TODAES), Volume 23, Issue 1

Article No.: 4, Pages 1 - 18

https://doi.org/10.1145/3084690

Published: 01 August 2017 Publication History

Abstract

Non-volatile memory technologies are among the most promising technologies for implementing the main memories and caches in future microprocessors and replacing the traditional DRAM and SRAM technologies. However, one of the most challenging design issues of the non-volatile memory technologies is the limited write. In this article, we first propose to exploit the narrow-width values to improve the lifetime of non-volatile last-level caches with word-level write variation reduction. Leading zeros masking scheme is proposed to reduce the write stress to the upper half of the narrow-width data. To balance the write variations between the upper half and the lower half of the narrow-width data, two swapping schemes, the swap on write (SW) and swap on replacement (SRepl), are proposed. Two existing optimization schemes, the multiple dirty bit (MDB) and read before write (RBW), are adopted with our word-level swapping design. To further reduce the write variation on the partition level, we propose to exploit the cache partitioning design to improve the lifetime. Based on the observation that different applications demonstrate different cache access (write) behaviors, we propose to partition the last-level cache for different applications and balance the write variations by partition swapping. Both software-based and hardware-based partitioning and swapping schemes are proposed and evaluated for different situations. Our experimental results show that both our word- and partition-level designs can improve the lifetime of the non-volatile caches effectively with low performance and energy overheads.

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Cited By

Sinha PBV KDas STavva V(2024)PROLONG: Priority based Write Bypassing Technique for Longer Lifetime in STT-RAM based LLCProceedings of the International Symposium on Memory Systems10.1145/3695794.3695803(89-103)Online publication date: 30-Sep-2024
https://dl.acm.org/doi/10.1145/3695794.3695803
Yang CChen YLiao HChang YLee J(2023)Auto-tuning Fixed-point Precision with TVM on RISC-V Packed SIMD ExtensionACM Transactions on Design Automation of Electronic Systems10.1145/356993928:3(1-21)Online publication date: 22-Mar-2023
https://dl.acm.org/doi/10.1145/3569939
Salahvarzi AKhosroanjam MMonazzah ABeitollahi HOgras UFazeli M(2023) WiSE: W hen Learning Ass i sts Resolving S TT-MRAM E fficiency Challenges IEEE Transactions on Emerging Topics in Computing10.1109/TETC.2022.316343811:1(43-55)Online publication date: 1-Jan-2023
https://doi.org/10.1109/TETC.2022.3163438
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Index Terms

Word- and Partition-Level Write Variation Reduction for Improving Non-Volatile Cache Lifetime
1. Computer systems organization
  1. Dependable and fault-tolerant systems and networks
    1. Processors and memory architectures
2. Hardware
  1. Integrated circuits
    1. Semiconductor memory
      1. Non-volatile memory

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Published In

cover image ACM Transactions on Design Automation of Electronic Systems

ACM Transactions on Design Automation of Electronic Systems Volume 23, Issue 1

January 2018

279 pages

ISSN:1084-4309

EISSN:1557-7309

DOI:10.1145/3129756

Editor:
Naehyuck Chang
Korea Advanced Institute of Science and Technology, Korea

Issue’s Table of Contents

Copyright © 2017 ACM.

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Association for Computing Machinery

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ACM Journals for the Design of Smart and Connected Systems

Publication History

Published: 01 August 2017

Accepted: 01 April 2017

Revised: 01 January 2017

Received: 01 September 2016

Published in TODAES Volume 23, Issue 1

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Cited By

Sinha PBV KDas STavva V(2024)PROLONG: Priority based Write Bypassing Technique for Longer Lifetime in STT-RAM based LLCProceedings of the International Symposium on Memory Systems10.1145/3695794.3695803(89-103)Online publication date: 30-Sep-2024
https://dl.acm.org/doi/10.1145/3695794.3695803
Yang CChen YLiao HChang YLee J(2023)Auto-tuning Fixed-point Precision with TVM on RISC-V Packed SIMD ExtensionACM Transactions on Design Automation of Electronic Systems10.1145/356993928:3(1-21)Online publication date: 22-Mar-2023
https://dl.acm.org/doi/10.1145/3569939
Salahvarzi AKhosroanjam MMonazzah ABeitollahi HOgras UFazeli M(2023) WiSE: W hen Learning Ass i sts Resolving S TT-MRAM E fficiency Challenges IEEE Transactions on Emerging Topics in Computing10.1109/TETC.2022.316343811:1(43-55)Online publication date: 1-Jan-2023
https://doi.org/10.1109/TETC.2022.3163438
Liang GYuan CYu MChen TChen KLee J(2022)The Support of MLIR HLS Adaptor for LLVM IRWorkshop Proceedings of the 51st International Conference on Parallel Processing10.1145/3547276.3548515(1-8)Online publication date: 29-Aug-2022
https://dl.acm.org/doi/10.1145/3547276.3548515
Shih MLai HLee CChen CLee J(2022)Register-Pressure Aware Predicator for Length Multiplier of RVVWorkshop Proceedings of the 51st International Conference on Parallel Processing10.1145/3547276.3548513(1-9)Online publication date: 29-Aug-2022
https://dl.acm.org/doi/10.1145/3547276.3548513
Mahdavi NRazaghian FFarbeh H(2022)An Architectural-Level Reliability Improvement Scheme in STT-MRAM Main MemoryMicroprocessors and Microsystems10.1016/j.micpro.2022.10446290(104462)Online publication date: Apr-2022
https://doi.org/10.1016/j.micpro.2022.104462
Mahdavi NRazaghian FFarbeh H(2022)Data block manipulation for error rate reduction in STT-MRAM based main memoryThe Journal of Supercomputing10.1007/s11227-022-04394-778:11(13342-13372)Online publication date: 1-Jul-2022
https://dl.acm.org/doi/10.1007/s11227-022-04394-7
Salahvarzi AMonazzah AFazeli MSkadron K(2021)NOSTalgy: Near-Optimum Run-Time STT-MRAM Quality-Energy Knob Management for Approximate Computing ApplicationsIEEE Transactions on Computers10.1109/TC.2020.298924370:3(414-427)Online publication date: 9-Feb-2021
https://dl.acm.org/doi/10.1109/TC.2020.2989243
Hosseini Monazzah ARahmani AMiele ADutt N(2020)CAST: Content-Aware STT-MRAM Cache Write Management for Different Levels of ApproximationIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2020.298632039:12(4385-4398)Online publication date: Dec-2020
https://doi.org/10.1109/TCAD.2020.2986320
Nath AKapoor H(2019)Write Variation Aware Cache Partitioning for Improved Lifetime in Non-volatile Caches2019 32nd International Conference on VLSI Design and 2019 18th International Conference on Embedded Systems (VLSID)10.1109/VLSID.2019.00091(425-430)Online publication date: Jan-2019
https://doi.org/10.1109/VLSID.2019.00091
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