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- ArticleJanuary 1996
Retiming with logic duplication transformation: theory and an application to partial scan
VLSID '96: Proceedings of the 9th International Conference on VLSI Design: VLSI in Mobile CommunicationJanuary 1996, Page 296A Abstract: Retiming when performed in conjunction with logic duplication results in many different circuit configurations that are not obtainable by retiming alone. These circuit configurations (we call RLD configurations) have significantly different ...
- research-articleMay 1974
Safe Asynchronous Sequential Circuits
IEEE Transactions on Computers (ITCO), Volume 23, Issue 5May 1974, Pages 494–500https://doi.org/10.1109/T-C.1974.223972A logic designer may inadvertently select the design equations in such a way that stable states other than those of the flow table are formed. During malfunctions, it is possible for the circuit to assume a set of stable states that are not members of ...