Retiming with logic duplication transformation: theory and an application to partial scan
Authors: 
A. Balakrishnan and S. T. ChakradharAuthors Info & Claims
A. Balakrishnan and S. T. ChakradharAuthors Info & ClaimsJanuary 1996
Page 296
Abstract
A Abstract: Retiming when performed in conjunction with logic duplication results in many different circuit configurations that are not obtainable by retiming alone. These circuit configurations (we call RLD configurations) have significantly different area, performance and testability characteristics. We develop a formal framework that allows consideration of all configurations that can be designed using the RLD transformation. The RLD configurations are represented as a feasible solution set of an integer linear program (ILP). The objective function of the ILP can be used to explore the trade off between different design and testability metrics. We Identify an approach to solve several useful special cases of the ILP in polynomial time. As far as we know, our framework is the first to treat RLD transformations in a formal way. To demonstrate the effectiveness of our framework, we consider the application of RLD transformation to partial scan. A recent technique determines the desired positions for scan flip-flops and then employs an RLD transformation to achieve this repositioning. No attempt is made to reduce the area overhead due to logic duplication. Using our RLD framework, we develop an efficient polynomial time algorithm to compute the desired RLD configuration for which the number of logic nodes duplicated is also minimized. Experimental results on large ISCAS 89 benchmark circuits are included to show that our algorithm is indeed very efficient.
References
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Information
Published In
January 1996
ISBN:0818672285
Copyright © Copyright (c) 1996 Institute of Electrical and Electronics Engineers, Inc. All rights reserved.
Publisher
IEEE Computer Society
United States
Publication History
Published: 03 January 1996
Author Tags
- RLD configurations
- RLD transformation
- circuit CAD
- flip-flops
- integer linear program
- integer programming
- integrated circuit design
- integrated logic circuits
- linear programming
- logic CAD
- logic design
- logic duplication transformation
- objective function
- partial scan application
- polynomial time algorithm
- retiming
- scan flip-flops
- sequential circuit design
- sequential circuits
- testability metrics
- timing
Qualifiers
- Article
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