research-article

Retiming synchronous circuitry

Authors:

Charles E. Leiserson and

James B. SaxeAuthors Info & Claims

Algorithmica, Volume 6, Issue 1-6

Pages 5 - 35

https://doi.org/10.1007/BF01759032

Published: 01 June 1991 Publication History

Abstract

This paper describes a circuit transformation calledretiming in which registers are added at some points in a circuit and removed from others in such a way that the functional behavior of the circuit as a whole is preserved. We show that retiming can be used to transform a given synchronous circuit into a more efficient circuit under a variety of different cost criteria. We model a circuit as a graph in which the vertex setV is a collection of combinational logic elements and the edge setE is the set of interconnections, each of which may pass through zero or more registers. We give anO(¦V∥E¦lg¦V¦) algorithm for determining an equivalent retimed circuit with the smallest possible clock period. We show that the problem of determining an equivalent retimed circuit with minimum state (total number of registers) is polynomial-time solvable. This result yields a polynomial-time optimal solution to the problem of pipelining combinational circuitry with minimum register cost. We also give a chacterization of optimal retiming based on an efficiently solvable mixed-integer linear-programming problem.

References

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Published In

cover image Algorithmica

Algorithmica Volume 6, Issue 1-6

Jun 1991

883 pages

ISSN:0178-4617

Issue’s Table of Contents

© Springer-Verlag New York Inc. 1991.

Publisher

Springer-Verlag

Berlin, Heidelberg

Publication History

Published: 01 June 1991

Revision received: 29 September 1988

Received: 15 October 1986

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Cited By

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https://dl.acm.org/doi/10.1109/ASP-DAC58780.2024.10473899
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