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- research-articleJune 2024
Scheduling for Cyber-Physical Systems with Heterogeneous Processing Units under Real-World Constraints
ICS '24: Proceedings of the 38th ACM International Conference on SupercomputingMay 2024, Pages 298–311https://doi.org/10.1145/3650200.3656625Cyber-physical systems (CPS) such as robots and self-driving cars pose strict physical requirements to avoid failure. The scheduling choices impact these requirements. This presents a challenge: How do we find efficient schedules for CPS with ...
- research-articleJune 2024
Secured-by-design systems-on-chip: a MBSE Approach
RSP '23: Proceedings of the 34th International Workshop on Rapid System PrototypingSeptember 2023, Article No.: 07, Pages 1–7https://doi.org/10.1145/3625223.3649277Security by Design (SbD) has gained increasing interest over the past decade. While iterative processes and legacy preservation aim to reduce costs and mitigate risks through continuity, SbD encourages a break in the way we do things with a simple idea: ...
- research-articleMarch 2023
Optimization of AI SoC with Compiler-assisted Virtual Design Platform
ISPD '23: Proceedings of the 2023 International Symposium on Physical DesignMarch 2023, Pages 187–193https://doi.org/10.1145/3569052.3578930As deep learning keeps evolving dramatically with rapidly increasing complexity, the demand for efficient hardware accelerators has become vital. However, the lack of software/hardware co-development toolchains makes designing AI SoCs (artificial ...
- invited-talkDecember 2022
A Scalable Methodology for Agile Chip Development with Open-Source Hardware Components
- Maico Cassel dos Santos,
- Tianyu Jia,
- Martin Cochet,
- Karthik Swaminathan,
- Joseph Zuckerman,
- Paolo Mantovani,
- Davide Giri,
- Jeff Jun Zhang,
- Erik Jens Loscalzo,
- Gabriele Tombesi,
- Kevin Tien,
- Nandhini Chandramoorthy,
- John-David Wellman,
- David Brooks,
- Gu-Yeon Wei,
- Kenneth Shepard,
- Luca P. Carloni,
- Pradip Bose
ICCAD '22: Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided DesignOctober 2022, Article No.: 20, Pages 1–9https://doi.org/10.1145/3508352.3561102We present a scalable methodology for the agile physical design of tile-based heterogeneous system-on-chip (SoC) architectures that simplifies the reuse and integration of open-source hardware components. The methodology leverages the regularity of the ...
- ArticleMarch 2023
TPCx-AI on NVIDIA Jetsons
Performance Evaluation and BenchmarkingSep 2022, Pages 49–66https://doi.org/10.1007/978-3-031-29576-8_4AbstractDespite their resource- and power-constrained nature, edge devices also exhibit an increase in the available compute and memory resources and heterogeneity, similar to the evolution of server hardware in the past decade. For example, NVIDIA Jetson ...
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- research-articleFebruary 2022
Improving Loop Parallelization by a Combination of Static and Dynamic Analyses in HLS
ACM Transactions on Reconfigurable Technology and Systems (TRETS), Volume 15, Issue 3Article No.: 31, Pages 1–31https://doi.org/10.1145/3501801High-level synthesis (HLS) can be used to create hardware accelerators for compute-intense software parts such as loop structures. Usually, this process requires significant amount of user interaction to steer kernel selection and optimizations. This can ...
- research-articleJanuary 2022
Performance and communication energy constrained embedded benchmark for fault tolerant core mapping onto NoC architectures
International Journal of Ad Hoc and Ubiquitous Computing (IJAHUC), Volume 41, Issue 22022, Pages 108–117https://doi.org/10.1504/ijahuc.2022.125427Due to the rapid growth of the components encapsulated on the on-chip architecture, the performance degradation and communication issues between the cores significantly impact NoC architecture. It also increases the possibility of core failures ...
- research-articleOctober 2021
Cohmeleon: Learning-Based Orchestration of Accelerator Coherence in Heterogeneous SoCs
MICRO '21: MICRO-54: 54th Annual IEEE/ACM International Symposium on MicroarchitectureOctober 2021, Pages 350–365https://doi.org/10.1145/3466752.3480065One of the most critical aspects of integrating loosely-coupled accelerators in heterogeneous SoC architectures is orchestrating their interactions with the memory hierarchy, especially in terms of navigating the various cache-coherence options: from ...
- research-articleJanuary 2021
A CAD approach for power supply noise aware floorplan in SoC
International Journal of High Performance Systems Architecture (IJHPSA), Volume 10, Issue 22021, Pages 64–69https://doi.org/10.1504/ijhpsa.2021.119148This paper deals for reduction of power supply noise with decoupling capacitor estimation and allocation using particle swarm optimisation (PSO) algorithm at the floorplanning stage of the physical design process. Decoupling capacitors are allocated ...
- keynoteSeptember 2020
Towards Self-Aware Systems-on-Chip Through Intelligent Cross-Layer Coordination
GLSVLSI '20: Proceedings of the 2020 on Great Lakes Symposium on VLSISeptember 2020, Page 137https://doi.org/10.1145/3386263.3409105Although there is a rich history of cross-layer design for embedded computing systems to achieve desired QoS, we are facing ever more challenges from the intertwined goals of energy- efficiency, thermal design constraints, as well as resilience to ...
- research-articleSeptember 2020
Chosen base‐point side‐channel attack on Montgomery ladder with x ‐only coordinate: with application to secp256k1
IET Information Security (ISE2), Volume 14, Issue 5September 2020, Pages 483–492https://doi.org/10.1049/iet-ifs.2018.5228This study revisits the side‐channel security of the elliptic curve cryptography (ECC) scalar multiplication implemented with Montgomery ladder. Focusing on a specific implementation that does not use the y ‐coordinate for point addition (ECADD) and ...
- research-articleNovember 2020
Chipyard - An integrated SoC research and implementation environment: invited
- Alon Amid,
- David Biancolin,
- Abraham Gonzalez,
- Daniel Grubb,
- Sagar Karandikar,
- Harrison Liew,
- Albert Magyar,
- Howard Mao,
- Albert Ou,
- Nathan Pemberton,
- Paul Rigge,
- Colin Schmidt,
- John Wright,
- Jerry Zhao,
- Jonathan Bachrach,
- Sophia Shao,
- Borivoje Nikolić,
- Krste Asanović
DAC '20: Proceedings of the 57th ACM/EDAC/IEEE Design Automation ConferenceJuly 2020, Article No.: 143, Pages 1–6Continued improvement in computing efficiency requires functional specialization of hardware designs. We present an agile design flow for custom SoCs using the Chipyard framework, an integrated SoC research and implementation environment for custom ...
- research-articleApril 2020
Spectrum shaping using NC‐OFDM for cognitive radio applications
IET Communications (CMU2), Volume 14, Issue 7Pages 1120–1128https://doi.org/10.1049/iet-com.2018.5945Cognitive radio (CR) is an innovative technology that supports dynamic spectrum access to utilise the spectrum more efficiently in an opportunistic manner without interfering with the licensed users. Multi‐carrier modulation techniques such as orthogonal ...
- research-articleOctober 2019
Dynamic and scalable runtime block-based multicast routing for networks on chips
NoCArc '19: Proceedings of the 12th International Workshop on Network on Chip ArchitecturesOctober 2019, Article No.: 10, Pages 1–6https://doi.org/10.1145/3356045.3360718Hardware multicast (one-to-many communication) support in Networks on Chips (NoCs) is beneficial for a wide range of applications. Multicast traffic is seen in applications using coherency protocols in distributed shared-memory systems, neural network ...
- research-articleMay 2019
System-on-a-Chip Design as a Platform for Teaching Design and Design Flow Integration
GLSVLSI '19: Proceedings of the 2019 Great Lakes Symposium on VLSIMay 2019, Pages 249–253https://doi.org/10.1145/3299874.3318000The design of microelectronic systems requires integration and cooperation across multiple disciplines, but most curriculum is taught in unconnected pieces. This makes the creation of manageable projects that reflect the design experience very difficult. ...
- research-articleJanuary 2019
An adaptive low power coding scheme for the NoC
International Journal of Advanced Intelligence Paradigms (IJAIP), Volume 13, Issue 3-42019, Pages 324–333https://doi.org/10.1504/ijaip.2019.101982Low power system design is important for system-on-chip design where communication takes place at higher data rate to realise the system functionality. Low power coding reduces energy by reducing self-switching activity or coupling switching activity. But ...
- research-articleMarch 2018
An Improved Cross-Coupled NAND Gates PUF for Bank IC Card
ICCSP 2018: Proceedings of the 2nd International Conference on Cryptography, Security and PrivacyMarch 2018, Pages 150–153https://doi.org/10.1145/3199478.3199493This paper presents some verifications and improved considerations of NAND PUF, which was introduced recently [1]. For embedded system such as IC cards, the secret data in memory is vulnerable, so it has to be encrypted and secured. PUF circuit is ...
- research-articleDecember 2017
Fault Injection for Test-Driven Development of Robust SoC Firmware
ACM Transactions on Embedded Computing Systems (TECS), Volume 17, Issue 1Article No.: 19, Pages 1–26https://doi.org/10.1145/3092943Robustness against errors in hardware must be considered from the very beginning of safety-critical system-on-chip firmware design. Therefore, we present fault injection for test-driven development (TDD) of robust firmware. As TDD is based on instant ...
- research-articleNovember 2016
Quantifying energy use in dense shared memory HPC node
E2SC '16: Proceedings of the 4th International Workshop on Energy Efficient SupercomputingNovember 2016, Pages 16–23In this paper we introduce a novel, dense, system-on-chip many-core Lenovo NeXtScale System® server based on the Cavium ThunderX® ARMv8 processor that was designed for performance, energy efficiency and programmability. ThunderX processor was designed ...
- research-articleOctober 2016
Rapid SoC prototyping utilizing quilt packaging technology for modular functional IC partitioning
RSP '16: Proceedings of the 27th International Symposium on Rapid System Prototyping: Shortening the Path from Specification to PrototypeOctober 2016, Pages 79–85https://doi.org/10.1145/2990299.2990313A microchip integration technology called Quilt Packaging (QP) enables rapid prototyping of complex SoCs and microwave/RF systems, as well as optical, power, and DSP applications. QP is a direct edge-to-edge chip-level interconnect technology that can ...