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- research-articleJanuary 2023
ETAP: Energy-aware Timing Analysis of Intermittent Programs
ACM Transactions on Embedded Computing Systems (TECS), Volume 22, Issue 2Article No.: 23, Pages 1–31https://doi.org/10.1145/3563216Energy harvesting battery-free embedded devices rely only on ambient energy harvesting that enables stand-alone and sustainable IoT applications. These devices execute programs when the harvested ambient energy in their energy reservoir is sufficient to ...
- invited-talkDecember 2022
Applying GNNs to Timing Estimation at RTL
ICCAD '22: Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided DesignOctober 2022, Article No.: 3, Pages 1–8https://doi.org/10.1145/3508352.3561095In the Electronic Design Automation (EDA) flow, signoff checks, such as timing analysis, are performed only after physical synthesis. Encountered timing violations cause re-iterations of the design flow. Hence, timing estimations at initial design ...
- research-articleOctober 2022
A comprehensive framework for the analysis of automotive systems
- Alessandro Cimatti,
- Sara Corfini,
- Luca Cristoforetti,
- Marco Di Natale,
- Alberto Griggio,
- Stefano Puri,
- Stefano Tonetta
MODELS '22: Proceedings of the 25th International Conference on Model Driven Engineering Languages and SystemsOctober 2022, Pages 379–389https://doi.org/10.1145/3550355.3552408Analysis models, technologies and tools are extensively used in the automotive domain to validate and optimize the design and implementation of SW systems. This is especially true for modern systems including advanced autonomous (and complex) features. ...
- research-articleAugust 2022
Timing macro modeling with graph neural networks
DAC '22: Proceedings of the 59th ACM/IEEE Design Automation ConferenceJuly 2022, Pages 1219–1224https://doi.org/10.1145/3489517.3530599Due to rapidly growing design complexity, timing macro modeling has been widely adopted to enable hierarchical and parallel timing analysis. The main challenge of timing macro modeling is to identify timing variant pins for achieving high timing accuracy ...
- research-articleJune 2022
A memory interference analysis using a formal timing analyzer (WIP)
LCTES 2022: Proceedings of the 23rd ACM SIGPLAN/SIGBED International Conference on Languages, Compilers, and Tools for Embedded SystemsJune 2022, Pages 146–150https://doi.org/10.1145/3519941.3535077Safety-critical applications require well-defined and documented timing behavior. These requirements shape the design and implementation of a timing analyzer based on a formal Instruction-Set Architecture (ISA) semantics and formal micro-architecture ...
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- research-articleJune 2022
Leveraging Machine Learning for Gate-level Timing Estimation Using Current Source Models and Effective Capacitance
GLSVLSI '22: Proceedings of the Great Lakes Symposium on VLSI 2022June 2022, Pages 77–83https://doi.org/10.1145/3526241.3530343With process technology scaling, accurate gate-level timing analysis becomes even more challenging. Highly resistive on-chip interconnects have an ever-increasing impact on timing, signals no longer resemble smooth saturated ramps, while gate-...
- research-articleJanuary 2022
Low-power Near-data Instruction Execution Leveraging Opcode-based Timing Analysis
ACM Transactions on Architecture and Code Optimization (TACO), Volume 19, Issue 2Article No.: 19, Pages 1–26https://doi.org/10.1145/3504005Traditional processor architectures utilize an external DRAM for data storage, while they also operate under worst-case timing constraints. Such designs are heavily constrained by the delay costs of the data transfer between the core pipeline and the DRAM,...
- research-articleSeptember 2021
Scenario-Aware Program Specialization for Timing Predictability
ACM Transactions on Architecture and Code Optimization (TACO), Volume 18, Issue 4Article No.: 54, Pages 1–26https://doi.org/10.1145/3473333The successful application of static program analysis strongly depends on flow facts of a program such as loop bounds, control-flow constraints, and operating modes. This problem heavily affects the design of real-time systems, since static program ...
- research-articleMarch 2021Best Paper
Machine Learning-Enabled High-Frequency Low-Power Digital Design Implementation At Advanced Process Nodes
ISPD '21: Proceedings of the 2021 International Symposium on Physical DesignMarch 2021, Pages 83–90https://doi.org/10.1145/3439706.3447043Relentless pursuit of high-frequency low-power designs at advanced nodes necessitate achieving signoff-quality timing and power during digital implementation to minimize any over-design. With growing design sizes (1--10M instances), full flow runtime is ...
- research-articleFebruary 2020
A Theoretical Foundation for Timing Synchronous Systems Using Asynchronous Structures
ACM Transactions on Design Automation of Electronic Systems (TODAES), Volume 25, Issue 2Article No.: 16, Pages 1–28https://doi.org/10.1145/3373355Timing of synchronous systems is an everlasting stumbling block to the booming demands for lower power consumption and higher operation speeds in the electronics industry. This hardship is aggravated by the growing levels of variability in state-of-the-...
- research-articleJuly 2019
Correct-by-Construction Parallelization of Hard Real-Time Avionics Applications on Off-the-Shelf Predictable Hardware
- Keryan Didier,
- Dumitru Potop-Butucaru,
- Guillaume Iooss,
- Albert Cohen,
- Jean Souyris,
- Philippe Baufreton,
- Amaury Graillat
ACM Transactions on Architecture and Code Optimization (TACO), Volume 16, Issue 3Article No.: 24, Pages 1–27https://doi.org/10.1145/3328799We present the first end-to-end modeling and compilation flow to parallelize hard real-time control applications while fully guaranteeing the respect of real-time requirements on off-the-shelf hardware. It scales to thousands of dataflow nodes and has ...
- research-articleJune 2019
Imprecision in WCET estimates due to library calls and how to reduce it (WIP paper)
LCTES 2019: Proceedings of the 20th ACM SIGPLAN/SIGBED International Conference on Languages, Compilers, and Tools for Embedded SystemsJune 2019, Pages 208–212https://doi.org/10.1145/3316482.3326353One of the main difficulties in estimating the Worst Case Execution Time (WCET) at the binary level is that machine instructions do not allow inferring call contexts as precisely as source code, since compiler optimizations obfuscate control flow and ...
- surveyJune 2019
A Survey of Timing Verification Techniques for Multi-Core Real-Time Systems
ACM Computing Surveys (CSUR), Volume 52, Issue 3Article No.: 56, Pages 1–38https://doi.org/10.1145/3323212This survey provides an overview of the scientific literature on timing verification techniques for multi-core real-time systems. It reviews the key results in the field from its origins around 2006 to the latest research published up to the end of ...
- research-articleJanuary 2019
SIMULTime: Context-sensitive timing simulation on intermediate code representation for rapid platform explorations
ASPDAC '19: Proceedings of the 24th Asia and South Pacific Design Automation ConferenceJanuary 2019, Pages 526–531https://doi.org/10.1145/3287624.3287625Nowadays, product lines are common practice in the embedded systems domain as they allow for substantial reductions in development costs and the time-to-market by a consequent application of design paradigms such as variability and structured reuse ...
- research-articleOctober 2018
Timing analysis of AVB Ethernet network using the Forward end-to-end Delay Analysis
RTNS '18: Proceedings of the 26th International Conference on Real-Time Networks and SystemsOctober 2018, Pages 223–233https://doi.org/10.1145/3273905.3273922Audio Video Bridging Ethernet (AVB) [1] is a standard developed by IEEE Audio Video Bridging Task Group based on switched-Ethernet. It is used in the automotive domain. AVB includes flow differentiation service using Fixed Priority (FP) policy. It ...
- research-articleMay 2018
Fast Timing Analysis of Non-Tree Clock Network with Shorted Wires
GLSVLSI '18: Proceedings of the 2018 Great Lakes Symposium on VLSIMay 2018, Pages 279–284https://doi.org/10.1145/3194554.3194598A non-tree clock network, such as crosslink and mesh, includes some shorted wires to reduce clock skew. A short-circuit current that flows through the shorted wires makes conventional static timing analysis (STA) inapplicable. Transistor-level simulation ...
- research-articleDecember 2017
Timing analysis of a middleware-based system
ARM '17: Proceedings of the 16th Workshop on Adaptive and Reflective MiddlewareDecember 2017, Article No.: 5, Pages 1–6https://doi.org/10.1145/3152881.3152886Component-based systems are often constructed with the help of a middleware layer that provides execution semantics for the components. If the implementations of the components use only the middleware services for concurrency, synchronization, and ...
- abstractApril 2017
Time Bands: A Software Approach for Timing Analysis on Resource Constrained Systems
ICPE '17: Proceedings of the 8th ACM/SPEC on International Conference on Performance EngineeringApril 2017, Pages 161–162https://doi.org/10.1145/3030207.3053665Timing analysis of embedded systems is an operation performed when there are tasks that have to execute with a well precise deadline, and need to be scheduled, such as those on real-time systems. The diffusion of embedded systems to different kind of ...
- research-articleMarch 2017
Optimizing temperature guardbands
DATE '17: Proceedings of the Conference on Design, Automation & Test in EuropeMarch 2017, Pages 175–180We introduce the first temperature guardbands optimization based on thermal-aware logic synthesis and thermal-aware timing analysis. The optimized guardbands are obtained solely due to using our so-called thermal-aware cell libraries together with ...
- research-articleDecember 2016
Non-enumerative Generation of Path Delay Distributions and Its Application to Critical Path Selection
ACM Transactions on Design Automation of Electronic Systems (TODAES), Volume 22, Issue 1Article No.: 17, Pages 1–21https://doi.org/10.1145/2940327A Monte Carlo-based approach is proposed capable of identifying in a non-enumerative and scalable manner the distributions that describe the delay of every path in a combinational circuit. Furthermore, a scalable approach to select critical paths from a ...