invited-talk

Applying GNNs to Timing Estimation at RTL

Authors:

Daniela Sánchez Lopera,

Wolfgang EckerAuthors Info & Claims

ICCAD '22: Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design

Article No.: 3, Pages 1 - 8

https://doi.org/10.1145/3508352.3561095

Published: 22 December 2022 Publication History

Abstract

In the Electronic Design Automation (EDA) flow, signoff checks, such as timing analysis, are performed only after physical synthesis. Encountered timing violations cause re-iterations of the design flow. Hence, timing estimations at initial design stages, such as Register Transfer Level (RTL), would increase the quality of the results and lower the flow iterations. Machine learning has been used to estimate the timing behavior of chip components. However, existing solutions map EDA objects to Euclidean data without considering that EDA objects are represented naturally as graphs. Recent advances in Graph Neural Networks (GNNs) motivate the mapping from EDA objects to graphs for design metric prediction tasks at different stages. This paper maps RTL designs to directed, featured graphs with multidimensional node and edge features. These are the input to GNNs for estimating component delays and slews. An in-house hardware generation framework and open-source EDA tools for ASIC synthesis are employed for collecting training data. Experiments over unseen circuits show that GNN-based models are promising for timing estimation, even when the features come from early RTL implementations. Based on estimated delays, critical areas of the design can be detected, and proper RTL micro-architectures can be chosen without running long design iterations.

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Cited By

Alcorta Lozano EGerstlauer ADeng CSun QZhang ZXu CWills LSanchez Lopera DEcker WGarg SHu JAl Faruque MHu X(2023)Special Session: Machine Learning for Embedded System DesignProceedings of the 2023 International Conference on Hardware/Software Codesign and System Synthesis10.1145/3607888.3608962(28-37)Online publication date: 17-Sep-2023
https://dl.acm.org/doi/10.1145/3607888.3608962
Sengupta PTyagi AChen YHu J(2023)Early Identification of Timing Critical RTL Components using ML based Path Delay Prediction2023 ACM/IEEE 5th Workshop on Machine Learning for CAD (MLCAD)10.1109/MLCAD58807.2023.10299879(1-6)Online publication date: 10-Sep-2023
https://doi.org/10.1109/MLCAD58807.2023.10299879
Zhu LGuo X(2023)Delay-Driven Physically-Aware Logic Synthesis with Informed Search2023 IEEE 41st International Conference on Computer Design (ICCD)10.1109/ICCD58817.2023.00057(327-335)Online publication date: 6-Nov-2023
https://doi.org/10.1109/ICCD58817.2023.00057
Show More Cited By

Index Terms

Applying GNNs to Timing Estimation at RTL
1. Computing methodologies
  1. Machine learning
2. Hardware
  1. Electronic design automation

Index terms have been assigned to the content through auto-classification.

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Published In

cover image ACM Conferences

ICCAD '22: Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design

October 2022

1467 pages

ISBN:9781450392174

DOI:10.1145/3508352

Conference Chair:
Tulika Mitra
National University of Singapore
,
Program Chairs:
Evangeline Young
The Chinese University of Hong Kong
,
Jinjun Xiong
University at Buffalo (UB)

Copyright © 2022 Owner/Author.

Permission to make digital or hard copies of part or all of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for third-party components of this work must be honored. For all other uses, contact the Owner/Author.

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Published: 22 December 2022

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ICCAD '22: IEEE/ACM International Conference on Computer-Aided Design

October 30 - November 3, 2022

California, San Diego

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Cited By

Alcorta Lozano EGerstlauer ADeng CSun QZhang ZXu CWills LSanchez Lopera DEcker WGarg SHu JAl Faruque MHu X(2023)Special Session: Machine Learning for Embedded System DesignProceedings of the 2023 International Conference on Hardware/Software Codesign and System Synthesis10.1145/3607888.3608962(28-37)Online publication date: 17-Sep-2023
https://dl.acm.org/doi/10.1145/3607888.3608962
Sengupta PTyagi AChen YHu J(2023)Early Identification of Timing Critical RTL Components using ML based Path Delay Prediction2023 ACM/IEEE 5th Workshop on Machine Learning for CAD (MLCAD)10.1109/MLCAD58807.2023.10299879(1-6)Online publication date: 10-Sep-2023
https://doi.org/10.1109/MLCAD58807.2023.10299879
Zhu LGuo X(2023)Delay-Driven Physically-Aware Logic Synthesis with Informed Search2023 IEEE 41st International Conference on Computer Design (ICCD)10.1109/ICCD58817.2023.00057(327-335)Online publication date: 6-Nov-2023
https://doi.org/10.1109/ICCD58817.2023.00057
Jiang I(2023)Lightning Talk: All Routes to Timing Closure2023 60th ACM/IEEE Design Automation Conference (DAC)10.1109/DAC56929.2023.10247801(1-2)Online publication date: 9-Jul-2023
https://doi.org/10.1109/DAC56929.2023.10247801
Zhu LGu YGuo X(2023)RC-GNN: Fast and Accurate Signoff Wire Delay Estimation with Customized Graph Neural Networks2023 IEEE 5th International Conference on Artificial Intelligence Circuits and Systems (AICAS)10.1109/AICAS57966.2023.10168562(1-5)Online publication date: 11-Jun-2023
https://doi.org/10.1109/AICAS57966.2023.10168562

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