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- Article
FlexCore: A Reconfigurable Processor Supporting Flexible, Dynamic Morphing
HIPC '15: Proceedings of the 2015 IEEE 22nd International Conference on High Performance Computing (HiPC)•December 2015, pp 30-39• https://doi.org/10.1109/HiPC.2015.37In the realm of desktop and server class processors, the prevailing trend is to use out-of-order superscalar cores that exploit the hidden instruction-level parallelism in a program. In superscalar designs, the performance (as measured by the IPC, ...
- research-article
MARSS: a full system simulator for multicore x86 CPUs
DAC '11: Proceedings of the 48th Design Automation Conference•June 2011, pp 1050-1055• https://doi.org/10.1145/2024724.2024954We present MARSS, an open source, fast, full system simulation tool built on QEMU to support cycle-accurate simulation of superscalar homogeneous and heterogeneous multicore x86 processors. MARSS includes detailed models of coherent caches, ...
- research-article
Selective writeback: reducing register file pressure and energy consumption
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Volume 16, Issue 6•June 2008, pp 650-661 • https://doi.org/10.1109/TVLSI.2008.2000243Much of the complexity in today's superscalar microprocessors stems from the need to maintain the speculatively produced results within the on-chip storage components until these results can be safely discarded without endangering the reconstruction of ...
- research-article
Predicting and Exploiting Transient Values for Reducing Register File Pressure and Energy Consumption
IEEE Transactions on Computers, Volume 57, Issue 1•January 2008, pp 82-95 • https://doi.org/10.1109/TC.2007.70785High-performance microprocessors use large, heavily-ported physical register files (RFs) to increase the instruction throughput. The high complexity and power dissipation of such RFs mainly stem from the need to maintain each and every result for a ...
- research-article
Early Register Deallocation Mechanisms Using Checkpointed Register Files
IEEE Transactions on Computers, Volume 55, Issue 9•September 2006, pp 1153-1166 • https://doi.org/10.1109/TC.2006.145Modern superscalar microprocessors need sizable register files to support a large number of in-flight instructions for exploiting instruction level parallelism (ILP). An alternative to building large register files is to use a smaller number of ...
- research-article
Energy Efficient Comparators for Superscalar Datapaths
IEEE Transactions on Computers, Volume 53, Issue 7•July 2004, pp 892-904 • https://doi.org/10.1109/TC.2004.29Modern superscalar datapaths use aggressive execution reordering to exploit instruction-level parallelism. Comparators, either explicit or embedded into content-addressable logic, are used extensively throughout such designs to implement several key out-...
- research-article
Complexity-Effective Reorder Buffer Designs for Superscalar Processors
IEEE Transactions on Computers, Volume 53, Issue 6•June 2004, pp 653-665 • https://doi.org/10.1109/TC.2004.5Abstract--All contemporary dynamically scheduled processors support register renaming to cope with false data dependencies. One of the ways to implement register renaming is to use the slots within the Reorder Buffer (ROB) as physical registers. In such ...
- research-article
Isolating Short-Lived Operands for Energy Reduction
IEEE Transactions on Computers, Volume 53, Issue 6•June 2004, pp 697-709 • https://doi.org/10.1109/TC.2004.11Abstract--A mechanism for reducing the power requirements in processors that use a separate (architectural) register file (ARF) for holding committed values is proposed in this paper. We exploit the notion of short-lived operands--values that target ...
