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Volume 1, Issue 2October 2007
Publisher:
  • Inderscience Publishers
  • World Trade Center Bldg, 29, route de Pre-Bois, Case Postale 896
  • Geneva 15
  • Switzerland
ISSN:1751-6528
EISSN:1751-6536
Reflects downloads up to 01 Sep 2024Bibliometrics
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article
A flexible processor for the characteristic 3 ηT pairing

The η<SUB align=right>T pairing is an efficient method for the calculation of the Tate pairing. In this paper, we describe the hardware implementation of the η<SUB align=right>T pairing on a supersingular elliptic curve of ...

article
Reconfiguration support for vector operations

A programmable vector processor and its implementation on a Field-Programmable Gate Array (FPGA) board are presented. This processor is composed of a vector core and a tightly coupled five-stage pipelined RISC scalar unit. It supports the IEEE 754 ...

article
Design of a router for network-on-chip

In this paper, we present several enhanced network techniques which are appropriate for VLSI implementation and have reduced complexity, high throughput and simple routing algorithm even if basic network problems such as deadlock and livelock are ...

article
Efficient finite field processor for GF(2<SUP align=right>163</SUP>) and its implementation

A high performance finite field processor for elliptic curve cryptography is presented. One of the contributions in this work is the modified Bit-Parallel Word-Serial (BPWS) finite field multiplication algorithm and its corresponding pipeline-fashion ...

article
An efficient fault tolerant mechanism to deal with permanent and transient failures in a network on chip

Recent advances in the silicon technology is enabling the VLSI chips to accommodate billions of transistors; leading toward incorporating hundreds of heterogeneous components on a single chip. However, it has been observed that the scalability of chips ...

article
Compact FPGA-based systolic array architecture suitable for vision systems

Motion estimation is a very computational demanding operation during video compression process in standards such as MPEG4, thus special hardware architectures are required to achieve real-time compression performance. The present work focuses on the ...

article
SPA resistant elliptic curve cryptosystem using addition chains

There has been a lot of interest in recent years in the problems faced by cryptosystems due to side channel attacks. Algorithms for elliptic curve point scalar multiplication such as the double-and-add method are prone to such attacks. By making use of ...

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