Modeling Cache Contention and Throughput of Multiprogrammed Manycore Processors
This paper proposes an analytical model for accurately predicting the impact of contention on cache miss rates. The focus is multiprogrammed workloads running on multithreaded manycore architectures. This work addresses a key challenge facing earlier ...
Structural Reduction Techniques for Logic-Chain Bridging Fault Diagnosis
This paper proposes four logic-chain bridging fault models, which involve one net in the combinational logic and the other net in the scan chain. Test results of logic-chain bridging faults, unlike existing scan chain fault models, depend on the ...
Variability-Aware Task Allocation for Energy-Efficient Quality of Service Provisioning in Embedded Streaming Multimedia Applications
Multimedia streaming applications running on next-generation parallel multiprocessor arrays in sub-45 nm technology face new challenges related to device and process variability, leading to performance and power variations across the cores. In this ...
Efficient 2-Approximation Algorithms for Computing 2-Connected Steiner Minimal Networks
For an undirected and weighted graph G=(V,E) and a terminal set S\subseteq V, the 2-connected Steiner minimal network (SMN) problem requires to compute a minimum-weight subgraph of G in which all terminals are 2-connected to each other. This problem has ...
A Fully Distributed Method to Detect and Reduce Cut Vertices in Large-Scale Overlay Networks
A cut vertex is defined as a network node whose removal increases the number of network components. Failure of a cut vertex disconnects a network component and downgrades the network performance. Overlay networks are resilient to the failure of random ...
A Pattern Generation Technique for Maximizing Switching Supply Currents Considering Gate Delays
Computation of peak supply current is central to power rail design and analysis of power supply switching noise. Traditionally, peak switching current from all CMOS gates is added together to compute peak supply current. This approach can be improved ...
A Comparison of FPGA and GPU for Real-Time Phase-Based Optical Flow, Stereo, and Local Image Features
Low-level computer vision algorithms have extreme computational requirements. In this work, we compare two real-time architectures developed using FPGA and GPU devices for the computation of phase-based optical flow, stereo, and local image features (...
High-Performance and Compact Architecture for Regular Expression Matching on FPGA
We present the design, implementation and evaluation of a high-performance architecture for regular expression matching (REM) on field-programmable gate array (FPGA). Each regular expression (regex) is first parsed into a concise token list ...
Scalable Tree-Based Architectures for IPv4/v6 Lookup Using Prefix Partitioning
Memory efficiency and dynamically updateable data structures for Internet Protocol (IP) lookup have regained much interest in the research community. In this paper, we revisit the classic tree-based approach for solving the longest prefix matching (LPM) ...
Homomorphic Property-Based Concurrent Error Detection of RSA: A Countermeasure to Fault Attack
Fault-based attacks, which recover secret keys by deliberately introducing fault(s) in cipher implementations and analyzing the faulty outputs, have been proved to be extremely powerful. In this paper, we propose a novel Concurrent Error Detection (CED) ...
Novel Convolutions Using First-Order Moments
This paper presents a novel fast algorithm for digital convolutions. It is able to compute arbitrary-length convolutions more efficiently via transforming the convolution into a first-order moment. Although many additions are required, the proposed ...
