IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

A cyber-physical system (CPS) is an integration of computation with physical processes whose behavior is defined by both computational and physical parts of the system. In this paper, we present a view of the challenges and opportunities for design ...

On-chip bus implementations must be bug-free and secure to provide the functionality and performance required by modern system-on-a-chip (SoC) designs. Regardless of the specific topology and protocol, bus behavior is never fully specified, meaning there ...

Counterfeit integrated circuits (IC) can be very harmful to the security and reliability of critical applications. Physical unclonable functions (PUFs) have been proposed as a mechanism for uniquely identifying ICs and thus reducing the prevalence of ...

Phase change memory (PCM), given its nonvolatility, potential high density, and low standby power, is a promising candidate to be used as main memory in next generation computer systems. However, to hide its shortcomings of limited endurance and slow ...

For complex datapaths, resource sharing can help reduce area consumption. Traditionally, resource sharing is applied when the same resource can be scheduled for different uses in different cycles, often resulting in a longer schedule. Multipumping is a ...

Double-gate devices, like independent-gate (IG) FinFET, have introduced new possibilities and challenges in synthesis of transistor networks. Existing factorization methods and graph-based optimizations are not actually the most effective way to generate ...

The effects of soft errors in processor cores have been widely studied. However, little has been published about soft errors in uncore components, such as the memory subsystem and I/O controllers, of a system-on-a-chip (SoC). In this paper, we study how ...

Accurate yield estimation under parametric variation is one of the most integral parts for robust and nonwasted circuit design. In particular, due to the significant impact of disparity on the high-replication circuit, precise yield estimation is ...

Guide-patterns (GPs) are critical to the construction of contacts and vias in directed self-assembly (DSA) lithography. Simulations can be used to verify GPs, but runtime is excessive. Instead, we categorize the shapes of GPs using a small number of ...

In deep-submicron very large scale integration manufacturing, dummy fills are widely applied to reduce topographic variations and improve layout pattern uniformity. However, the introduction of dummy fills may impact the wire electrical properties, such ...

A distance metric of patterns is crucial to hotspot cluster analysis and classification. In this paper, we propose an improved tangent space (ITS)-based distance metric for hotspot cluster analysis and classification. The proposed distance metric is an ...

With CMOS scaling beyond 14 nm, reliability is a major concern for IC manufacturers. Reliability-aware design has a non-negligible overhead and cannot account for user experience in mobile devices. An alternative is dynamic reliability management (DRM), ...

Scan test data compression is widely used in industry to reduce test data volume (TDV) and test application time (TAT). This paper shows how multiple scan chain expansion ratios can help to obtain high test data compression in system-on-chips. Scan chains ...

Due to the emergence of extremely high density memory along with the growing number of embedded memories, memory yield is an important issue. Memory self-repair using redundancies to increase the yield of memories is widely used. Because high density ...