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L4 Microkernels: The Lessons from 20 Years of Research and Deployment
The L4 microkernel has undergone 20 years of use and evolution. It has an active user and developer community, and there are commercial versions that are deployed on a large scale and in safety-critical systems. In this article we examine the lessons ...
Designing Future Warehouse-Scale Computers for Sirius, an End-to-End Voice and Vision Personal Assistant
- Johann Hauswald,
- Michael A. Laurenzano,
- Yunqi Zhang,
- Hailong Yang,
- Yiping Kang,
- Cheng Li,
- Austin Rovinski,
- Arjun Khurana,
- Ronald G. Dreslinski,
- Trevor Mudge,
- Vinicius Petrucci,
- Lingjia Tang,
- Jason Mars
As user demand scales for intelligent personal assistants (IPAs) such as Apple’s Siri, Google’s Google Now, and Microsoft’s Cortana, we are approaching the computational limits of current datacenter (DC) architectures. It is an open question how future ...
Identifying Power-Efficient Multicore Cache Hierarchies via Reuse Distance Analysis
To enable performance improvements in a power-efficient manner, computer architects have been building CPUs that exploit greater amounts of thread-level parallelism. A key consideration in such CPUs is properly designing the on-chip cache hierarchy. ...
