This paper outlines a case study at SGS-Thomson Microelectronicson the development of a firmware development environment in co-operationwith Thomson Consumer Electronics Components. Theenviornment is for an embedded processor used for audiodecompression ...

Novel test bench techniques are required to cope with afunctional test complexity which is predicted to grow muchmore strongly than design complexity. Our test benchapproach attacks this complexity by using a stronghierarchical architecture, application ...

This paper presents a system capable of static and dynamic simulationsof heterogeneous opto-electronic systems. It is capable ofmodeling Gaussian optical signal propagation with mechanicaltolerancing at the system level. We present results which ...

We propose an iterative optimization approach for mixedmacro-cell and standard-cell placement, which minimizes the chipsize and interconnection wire length at the same time. We present abranch-and-bound algorithm which efficiently searches for the ...

In this paper we present a novel formulation for thenet-based timing-driven placement problem.The new formulationperforms budgeting (net delay upper bounds) andplacement modification simultaneously thus alleviates theproblem of going back-and-forth ...

The "quadratic placement" methodology is rooted in [Module Placement Based on Resistive Network Optimization, Proud: A Sea-Of-Gate Placement Algorithm, A Combined Force and Cut Algorithm for Hierarchical VLSI Layout]and is reputedly used in many ...

This is a survey on the algorithms which are part ofa program for flat placement of large-scale VLSI processorchips. The basis is a quadratic optimization approachcombined with a new quadrisection algorithm.In contrast to most previous quadratic ...

The biggest obstacle in the formal verification of large designs istheir very large state spaces, which cannot be handled even bytechniques such as implicit state space traversal. The only viablesolution in most cases is validation by functional ...

Formally verifying properties of signals in a circuit hasseveral applications in an equivalence checking based formalverification flow.In a hierarchical design, functionalityis divided across blocks.This necessitates the useof constraints on input ...

Extending the applicability of reachability analysis to large andreal circuits is a key issue.In fact they are still limited forthe following reasons: peak BDD size during image computation,BDD explosion for representing state sets and very ...

In this paper, we describe a full customCMOS design methodology and supporting CADtechnologies used to develop ALPHA and StrongARMmicroprocessors at Digital Semiconductor. The paper issubdivided into four parts, starting with a description ofthe design ...

Sub-half-micron process technologies are creating a fundamentalshift in the problems faced by IC designers andfabricators.As geometries shrink, signal integrity (SI)and noise play a critical role in determining IC performance.Without accurate ...

In was projected by the National TechnologyRoadmap for Semiconductors that by the year 1998 thefeature size will shrink to 0.25μm and the chips maycontain as many as 28 million transistors.As the widthof wires shrinks, resistance increases more rapidly ...

For a given throughput constrained system-level specification,we present a design flow and an algorithm to select software(general purpose processors) and hardware components,and then partition and pipeline the specification amongstthe selected ...

In this paper we present a novel compiler-directed approach tosystem-level partitioning for a given description of system functionalityin a hardware description language (HDL). The algorithmis based on a definition-use analysis of the storage in the ...

Hardware-software co-synthesis is the process ofpartitioning an embedded system specification into hardware andsoftware modules to meet performance, power and cost goals. Inthis paper, we present a co-synthesis algorithm which starts withperiodic task ...

We present a system-level approach for power optimization undera set of user specified costs and timing constraints of hard real-timedesigns. The approach optimizes all three degrees of freedom forpower minimization, namely switching activity, effective ...

The performance of micro-electro-mechanical systemsdepends on the interaction between electrical, mechanical,and fluidic forces. Simulating this coupled problem is made moredifficult by the fact that most MEMS devices are innately three-dimensionaland ...

In order to efficiently design complex microelectromechanicalsystems (MEMS) having large numbers of multi-domain components,a hierarchically structured design approach that iscompatible with standard IC design is needed. A graphical-basedschematic, or ...

New design tools and automation strategies are neededto create robust, cost-effective, and manufacturable micro-machineddevices and systems. Some of the design automationissues include mixed-technology simulation, materialproperty prediction in the ...