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Disjunctive partitioning and partial iterative squaring: an effective approach for symbolic traversal of large circuits

Published: 13 June 1997 Publication History

Abstract

Extending the applicability of reachability analysis to large andreal circuits is a key issue.In fact they are still limited forthe following reasons: peak BDD size during image computation,BDD explosion for representing state sets and very highsequential depth.Following the promising trend of partitioning and problem decomposition,we present a new approach based on a disjunctivepartitioned transition relation and on an improved iterativesquaring.In this approach a Finite State Machine is decomposedand traversed one "functioning-mode" at a time bymeans of the "disjunctive" partitioned approach.The overall algorithm aims at lowering the intermediate peakBDD size pushing further reachability analysis.Experimentson a few industrial circuits containing counters and on somelarge benchmarks show the feasibility of the approach.

References

[1]
K. Ravi, F. Somenzi, "High-Density Reachability Analysis," in Proc. IEEE/ACM ICCAD'95, pp. 154- 158, November 1995
[2]
G. Cabodi, P. Camurati, S. Quer, "Improved Reachability Analysis of Large Finite State Machine," in Proc. IEEE/ACM ICCAD'96, pp. a54-a60, November 1996
[3]
J.R. Butch, E.M. Clarke, D.E. Long, K.L. McMillan, D.L. Dill: "Symbolic Model Checking for Sequential Circuit Verification," lEEE-Trar~saction on CAD, pp. 401-424, Volume 13, Number 4, April 1994
[4]
J.R. Butch, E.M. Clarke, D.E. Long: "Representing Circuits More Efficiently in Symbolic Model Checking," in Proc. A CM/IEEE DAC'91, pp. 403-407, June 1991
[5]
R. I-Iojati, S.C. Krishnan, R.K. Brayton, "Early Quantification and Partitioned Transition Relation," in Proc. IEEE ICCD'96, pp. 12-19, October 1996
[6]
H. Cho, G.D. I-Iachtel, E. Macii, M. Poncino, K. Ravi, F. Somenzi, "Approximate Finite State Machine Traversal: Extensions and New Results," in Proc. IWLS'95, May 1995
[7]
M68HCll Reference Manual, Motorola inc., 1991
[8]
G. Cabodi, P. Camurati, L. Lavagno, S. Quer, "Synthesis and verification of counters based on symbolic techniques," in Proc. EDAA/1EEE/ACM ED~TC'97, pp. 176-181, March 1997

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cover image ACM Conferences
DAC '97: Proceedings of the 34th annual Design Automation Conference
June 1997
788 pages
ISBN:0897919203
DOI:10.1145/266021
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 13 June 1997

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DAC97: The 34th Design Automation Conference
June 9 - 13, 1997
California, Anaheim, USA

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DAC '97 Paper Acceptance Rate 139 of 400 submissions, 35%;
Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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  • (2010)Computing argumentation in polynomial number of BDD operationsProceedings of the 7th international conference on Argumentation in Multi-Agent Systems10.1007/978-3-642-21940-5_16(268-285)Online publication date: 10-May-2010
  • (2009)Model checking sequential software programs via mixed symbolic analysisACM Transactions on Design Automation of Electronic Systems10.1145/1455229.145523914:1(1-26)Online publication date: 23-Jan-2009
  • (2008)Efficient guided symbolic reachability using reachability expressionsInternational Journal on Software Tools for Technology Transfer (STTT)10.5555/3220900.322111510:2(113-129)Online publication date: 1-Mar-2008
  • (2008)Efficient guided symbolic reachability using reachability expressionsInternational Journal on Software Tools for Technology Transfer10.1007/s10009-007-0057-710:2(113-129)Online publication date: 8-Jan-2008
  • (2007)Disjunctive image computation for software verificationACM Transactions on Design Automation of Electronic Systems10.1145/1230800.123080212:2(10-es)Online publication date: 1-Apr-2007
  • (2006)Disjunctive image computation for embedded software verificationProceedings of the conference on Design, automation and test in Europe: Proceedings10.5555/1131481.1131815(1205-1210)Online publication date: 6-Mar-2006
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  • (2006)Fast falsification based on symbolic bounded property checkingProceedings of the 43rd annual Design Automation Conference10.1145/1146909.1147181(1077-1082)Online publication date: 24-Jul-2006
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