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- research-articleMay 2024JUST ACCEPTED
Characterizing and Optimizing LDPC Performance on 3D NAND Flash Memories
ACM Transactions on Architecture and Code Optimization (TACO), Just Accepted https://doi.org/10.1145/3663478With the development of NAND flash memories’ bit density and stacking technologies, while storage capacity keeps increasing, the issue of reliability becomes increasingly prominent. Low-density parity check (LDPC) code, as a robust error-correcting code, ...
- research-articleJanuary 2024
WA-Zone: Wear-Aware Zone Management Optimization for LSM-Tree on ZNS SSDs
- Linbo Long,
- Shuiyong He,
- Jingcheng Shen,
- Renping Liu,
- Zhenhua Tan,
- Congming Gao,
- Duo Liu,
- Kan Zhong,
- Yi Jiang
ACM Transactions on Architecture and Code Optimization (TACO), Volume 21, Issue 1Article No.: 16, Pages 1–23https://doi.org/10.1145/3637488ZNS SSDs divide the storage space into sequential-write zones, reducing costs of DRAM utilization, garbage collection, and over-provisioning. The sequential-write feature of zones is well-suited for LSM-based databases, where random writes are organized ...
- research-articleAugust 2023
- research-articleAugust 2021
Low I/O Intensity-aware Partial GC Scheduling to Reduce Long-tail Latency in SSDs
- Zhibing Sha,
- Jun Li,
- Lihao Song,
- Jiewen Tang,
- Min Huang,
- Zhigang Cai,
- Lianju Qian,
- Jianwei Liao,
- Zhiming Liu
ACM Transactions on Architecture and Code Optimization (TACO), Volume 18, Issue 4Article No.: 46, Pages 1–25https://doi.org/10.1145/3460433This article proposes a low I/O intensity-aware scheduling scheme on garbage collection (GC) in SSDs for minimizing the I/O long-tail latency to ensure I/O responsiveness. The basic idea is to assemble partial GC operations by referring to several ...
- research-articleDecember 2018
SCORE: A Novel Scheme to Efficiently Cache Overlong ECCs in NAND Flash Memory
ACM Transactions on Architecture and Code Optimization (TACO), Volume 15, Issue 4Article No.: 60, Pages 1–25https://doi.org/10.1145/3291052Technology scaling and program/erase cycling result in an increasing bit error rate in NAND flash storage. Some solid state drives (SSDs) adopt overlong error correction codes (ECCs), whose redundancy size exceeds the spare area limit of flash pages, to ...
- research-articleMay 2018
ReveNAND: A Fast-Drift-Aware Resilient 3D NAND Flash Design
ACM Transactions on Architecture and Code Optimization (TACO), Volume 15, Issue 2Article No.: 17, Pages 1–26https://doi.org/10.1145/3184744The paradigm shift from planar (two dimensional (2D)) to vertical (three-dimensional (3D)) models has placed the NAND flash technology on the verge of a design evolution that can handle the demands of next-generation storage applications. However, it ...