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ReveNAND: A Fast-Drift-Aware Resilient 3D NAND Flash Design

Authors:

Mustafa M. Shihab,

Myoungsoo Jung,

Mahmut KandemirAuthors Info & Claims

ACM Transactions on Architecture and Code Optimization (TACO), Volume 15, Issue 2

Article No.: 17, Pages 1 - 26

https://doi.org/10.1145/3184744

Published: 01 May 2018 Publication History

Abstract

The paradigm shift from planar (two dimensional (2D)) to vertical (three-dimensional (3D)) models has placed the NAND flash technology on the verge of a design evolution that can handle the demands of next-generation storage applications. However, it also introduces challenges that may obstruct the realization of such 3D NAND flash. Specifically, we observed that the fast threshold drift (fast-drift) in a charge-trap flash-based 3D NAND cell can make it lose a critical fraction of the stored charge relatively soon after programming and generate errors.

In this work, we first present an elastic read reference (V_Ref) scheme (ERR) for reducing such errors in ReveNAND—our fast-drift aware 3D NAND design. To address the inherent limitation of the adaptive V_Ref, we introduce a new intra-block page organization (hitch-hike) that can enable stronger error correction for the error-prone pages. In addition, we propose a novel reinforcement-learning-based smart data refill scheme (iRefill) to counter the impact of fast-drift with minimum performance and hardware overhead. Finally, we present the first analytic model to characterize fast-drift and evaluate its system-level impact. Our results show that, compared to conventional 3D NAND design, our ReveNAND can reduce fast-drift errors by 87%, on average, and can lower the ECC latency and energy overheads by 13× and 10×, respectively.

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Cited By

Kim BSeo GKim M(2024)Smart Electrical Screening Methodology for Channel Hole Defects of 3D Vertical NAND (VNAND) Flash MemoryEng10.3390/eng50100275:1(495-512)Online publication date: 19-Mar-2024
https://doi.org/10.3390/eng5010027
Kim BKim M(2023)LazyRS: Improving the Performance and Reliability of High-Capacity TLC/QLC Flash-Based Storage Systems Using Lazy ReprogrammingElectronics10.3390/electronics1204084312:4(843)Online publication date: 7-Feb-2023
https://doi.org/10.3390/electronics12040843
Yang SZhao XXie KZhan XWu JChen J(2023)One-shot Read Processing to Enhance Cold Data Retention in Charge-trap TLC 3D NAND Flash2023 IEEE 15th International Conference on ASIC (ASICON)10.1109/ASICON58565.2023.10396612(1-4)Online publication date: 24-Oct-2023
https://doi.org/10.1109/ASICON58565.2023.10396612
Show More Cited By

Index Terms

ReveNAND: A Fast-Drift-Aware Resilient 3D NAND Flash Design
1. Hardware
2. Information systems
  1. Information storage systems
    1. Information storage technologies
      1. Storage class memory
        Flash memory

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Published In

cover image ACM Transactions on Architecture and Code Optimization

ACM Transactions on Architecture and Code Optimization Volume 15, Issue 2

June 2018

251 pages

ISSN:1544-3566

EISSN:1544-3973

DOI:10.1145/3212710

Editor:
Koen De Bosschere
Ghent University

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Copyright © 2018 ACM.

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Association for Computing Machinery

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Publication History

Published: 01 May 2018

Accepted: 01 January 2018

Revised: 01 December 2017

Received: 01 June 2017

Published in TACO Volume 15, Issue 2

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Cited By

Kim BSeo GKim M(2024)Smart Electrical Screening Methodology for Channel Hole Defects of 3D Vertical NAND (VNAND) Flash MemoryEng10.3390/eng50100275:1(495-512)Online publication date: 19-Mar-2024
https://doi.org/10.3390/eng5010027
Kim BKim M(2023)LazyRS: Improving the Performance and Reliability of High-Capacity TLC/QLC Flash-Based Storage Systems Using Lazy ReprogrammingElectronics10.3390/electronics1204084312:4(843)Online publication date: 7-Feb-2023
https://doi.org/10.3390/electronics12040843
Yang SZhao XXie KZhan XWu JChen J(2023)One-shot Read Processing to Enhance Cold Data Retention in Charge-trap TLC 3D NAND Flash2023 IEEE 15th International Conference on ASIC (ASICON)10.1109/ASICON58565.2023.10396612(1-4)Online publication date: 24-Oct-2023
https://doi.org/10.1109/ASICON58565.2023.10396612
Jia MKong YZhan XZhang MWu FChen J(2022)Optimal Program-Read Schemes Toward Highly Reliable Open Block Operations in 3-D Charge-Trap NAND Flash MemoryIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2021.313490041:11(4797-4807)Online publication date: 1-Nov-2022
https://dl.acm.org/doi/10.1109/TCAD.2021.3134900
Du YLiu WGao YAusavarungnirun R(2021)Observation and Optimization on Garbage Collection of Flash Memories: The View in Performance CliffMicromachines10.3390/mi1207084612:7(846)Online publication date: 20-Jul-2021
https://doi.org/10.3390/mi12070846
Zhang JKwon MSwift MJung MNoh SWelch B(2020)Scalable parallel flash firmware for many-core architecturesProceedings of the 18th USENIX Conference on File and Storage Technologies10.5555/3386691.3386704(121-136)Online publication date: 24-Feb-2020
https://dl.acm.org/doi/10.5555/3386691.3386704
Li QShi LDi YGao CJi CLiang YXue C(2020)Process Variation Aware Read Performance Improvement for LDPC-Based nand Flash MemoryIEEE Transactions on Reliability10.1109/TR.2019.289328769:1(310-321)Online publication date: Mar-2020
https://doi.org/10.1109/TR.2019.2893287
Huang PLiu YZhang XSiegel PHaratsch E(2020)Syndrome-Coupled Rate-Compatible Error-Correcting Codes: Theory and ApplicationIEEE Transactions on Information Theory10.1109/TIT.2020.296643966:4(2311-2330)Online publication date: Apr-2020
https://doi.org/10.1109/TIT.2020.2966439

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