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- research-articleJanuary 2025JUST ACCEPTED
Unveiling and Evaluating Vulnerabilities in Branch Predictors via a Three-Step Modeling Methodology
ACM Transactions on Architecture and Code Optimization (TACO), Just Accepted https://doi.org/10.1145/3711923With the emergence and proliferation of microarchitectural attacks targeting branch predictors, the once-established security boundary in computer systems and architectures is facing unprecedented challenges. This paper introduces an innovative branch ...
- research-articleNovember 2024JUST ACCEPTED
ShieldCXL: A Practical Obliviousness Support with Sealed CXL Memory
ACM Transactions on Architecture and Code Optimization (TACO), Just Accepted https://doi.org/10.1145/3703354The CXL (Compute Express Link) technology is an emerging memory interface with high-level commands. Recent studies applied the CXL memory expanding technique to mitigate the capacity limitation of the conventional DDRx memory. Unlike the prior studies to ...
- research-articleOctober 2024JUST ACCEPTED
- research-articleMay 2024
Camouflage: Utility-Aware Obfuscation for Accurate Simulation of Sensitive Program Traces
ACM Transactions on Architecture and Code Optimization (TACO), Volume 21, Issue 2Article No.: 36, Pages 1–23https://doi.org/10.1145/3650110Trace-based simulation is a widely used methodology for system design exploration. It relies on realistic traces that represent a range of behaviors necessary to be evaluated, containing a lot of information about the application, its inputs and the ...
- research-articleFebruary 2024
Coherence Attacks and Countermeasures in Interposer-based Chiplet Systems
ACM Transactions on Architecture and Code Optimization (TACO), Volume 21, Issue 2Article No.: 23, Pages 1–25https://doi.org/10.1145/3633461Industry is moving towards large-scale hardware systems that bundle processor cores, memories, accelerators, and so on. via 2.5D integration. These components are fabricated separately as chiplets and then integrated using an interposer as an interconnect ...
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- research-articleJanuary 2024
Hardware-hardened Sandbox Enclaves for Trusted Serverless Computing
ACM Transactions on Architecture and Code Optimization (TACO), Volume 21, Issue 1Article No.: 13, Pages 1–25https://doi.org/10.1145/3632954In cloud-based serverless computing, an application consists of multiple functions provided by mutually distrusting parties. For secure serverless computing, the hardware-based trusted execution environment (TEE) can provide strong isolation among ...
- research-articleFebruary 2023
SpecTerminator: Blocking Speculative Side Channels Based on Instruction Classes on RISC-V
ACM Transactions on Architecture and Code Optimization (TACO), Volume 20, Issue 1Article No.: 15, Pages 1–26https://doi.org/10.1145/3566053In modern processors, speculative execution has significantly improved the performance of processors, but it has also introduced speculative execution vulnerabilities. Recent defenses are based on the delayed execution to block various speculative side ...
- research-articleNovember 2022
Delay-on-Squash: Stopping Microarchitectural Replay Attacks in Their Tracks
ACM Transactions on Architecture and Code Optimization (TACO), Volume 20, Issue 1Article No.: 9, Pages 1–24https://doi.org/10.1145/3563695MicroScope and other similar microarchitectural replay attacks take advantage of the characteristics of speculative execution to trap the execution of the victim application in a loop, enabling the attacker to amplify a side-channel attack by executing it ...
- research-articleDecember 2021
SecNVM: An Efficient and Write-Friendly Metadata Crash Consistency Scheme for Secure NVM
ACM Transactions on Architecture and Code Optimization (TACO), Volume 19, Issue 1Article No.: 8, Pages 1–26https://doi.org/10.1145/3488724Data security is an indispensable part of non-volatile memory (NVM) systems. However, implementing data security efficiently on NVM is challenging, since we have to guarantee the consistency of user data and the related security metadata. Existing ...
- research-articleJuly 2021
Towards Enhanced System Efficiency while Mitigating Row Hammer
ACM Transactions on Architecture and Code Optimization (TACO), Volume 18, Issue 4Article No.: 40, Pages 1–26https://doi.org/10.1145/3458749In recent years, DRAM-based main memories have become susceptible to the Row Hammer (RH) problem, which causes bits to flip in a row without accessing them directly. Frequent activation of a row, called an aggressor row, causes its adjacent rows’ (victim)...
- research-articleDecember 2020
SPX64: A Scratchpad Memory for General-purpose Microprocessors
- Abhishek Singh,
- Shail Dave,
- Pantea Zardoshti,
- Robert Brotzman,
- Chao Zhang,
- Xiaochen Guo,
- Aviral Shrivastava,
- Gang Tan,
- Michael Spear
ACM Transactions on Architecture and Code Optimization (TACO), Volume 18, Issue 1Article No.: 14, Pages 1–26https://doi.org/10.1145/3436730General-purpose computing systems employ memory hierarchies to provide the appearance of a single large, fast, coherent memory. In special-purpose CPUs, programmers manually manage distinct, non-coherent scratchpad memories. In this article, we combine ...
- research-articleDecember 2020
SGXL: Security and Performance for Enclaves Using Large Pages
ACM Transactions on Architecture and Code Optimization (TACO), Volume 18, Issue 1Article No.: 12, Pages 1–25https://doi.org/10.1145/3433983Intel’s SGX architecture offers clients of public cloud computing platforms the ability to create hardware-protected enclaves whose contents are protected from privileged system software. However, SGX relies on system software for enclave memory ...
- research-articleNovember 2020
On Architectural Support for Instruction Set Randomization
- George Christou,
- Giorgos Vasiliadis,
- Vassilis Papaefstathiou,
- Antonis Papadogiannakis,
- Sotiris Ioannidis
ACM Transactions on Architecture and Code Optimization (TACO), Volume 17, Issue 4Article No.: 36, Pages 1–26https://doi.org/10.1145/3419841Instruction Set Randomization (ISR) is able to protect against remote code injection attacks by randomizing the instruction set of each process. Thereby, even if an attacker succeeds to inject code, it will fail to execute on the randomized processor. ...
- research-articleAugust 2020
Securing Branch Predictors with Two-Level Encryption
ACM Transactions on Architecture and Code Optimization (TACO), Volume 17, Issue 3Article No.: 21, Pages 1–25https://doi.org/10.1145/3404189Modern processors rely on various speculative mechanisms to meet performance demand. Branch predictors are one of the most important micro-architecture components to deliver performance. However, they have been under heavy scrutiny because of recent ...
- research-articleNovember 2019
Exploiting Bank Conflict-based Side-channel Timing Leakage of GPUs
ACM Transactions on Architecture and Code Optimization (TACO), Volume 16, Issue 4Article No.: 42, Pages 1–24https://doi.org/10.1145/3361870To prevent information leakage during program execution, modern software cryptographic implementations target constant-time function, where the number of instructions executed remains the same when program inputs change. However, the underlying ...
- research-articleAugust 2019
Side-channel Timing Attack of RSA on a GPU
ACM Transactions on Architecture and Code Optimization (TACO), Volume 16, Issue 3Article No.: 32, Pages 1–18https://doi.org/10.1145/3341729To increase computation throughput, general purpose Graphics Processing Units (GPUs) have been leveraged to accelerate computationally intensive workloads. GPUs have been used as cryptographic engines, improving encryption/decryption throughput and ...
- research-articleMarch 2019
Memory-Side Protection With a Capability Enforcement Co-Processor
- Leonid Azriel,
- Lukas Humbel,
- Reto Achermann,
- Alex Richardson,
- Moritz Hoffmann,
- Avi Mendelson,
- Timothy Roscoe,
- Robert N. M. Watson,
- Paolo Faraboschi,
- Dejan Milojicic
ACM Transactions on Architecture and Code Optimization (TACO), Volume 16, Issue 1Article No.: 5, Pages 1–26https://doi.org/10.1145/3302257Byte-addressable nonvolatile memory (NVM) blends the concepts of storage and memory and can radically improve data-centric applications, from in-memory databases to graph processing. By enabling large-capacity devices to be shared across multiple ...
- research-articleNovember 2018
Automated Software Protection for the Masses Against Side-Channel Attacks
ACM Transactions on Architecture and Code Optimization (TACO), Volume 15, Issue 4Article No.: 47, Pages 1–27https://doi.org/10.1145/3281662We present an approach and a tool to answer the need for effective, generic, and easily applicable protections against side-channel attacks. The protection mechanism is based on code polymorphism, so that the observable behaviour of the protected ...
- research-articleNovember 2018
RAGuard: An Efficient and User-Transparent Hardware Mechanism against ROP Attacks
ACM Transactions on Architecture and Code Optimization (TACO), Volume 15, Issue 4Article No.: 50, Pages 1–21https://doi.org/10.1145/3280852Control-flow integrity (CFI) is a general method for preventing code-reuse attacks, which utilize benign code sequences to achieve arbitrary code execution. CFI ensures that the execution of a program follows the edges of its predefined static Control-...
- research-articleDecember 2017
Compiler-Assisted Loop Hardening Against Fault Attacks
ACM Transactions on Architecture and Code Optimization (TACO), Volume 14, Issue 4Article No.: 36, Pages 1–25https://doi.org/10.1145/3141234Secure elements widely used in smartphones, digital consumer electronics, and payment systems are subject to fault attacks. To thwart such attacks, software protections are manually inserted requiring experts and time. The explosion of the Internet of ...