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- research-articleJanuary 2019
Performance-Aware Test Scheduling for Diagnosing Coexistent Channel Faults in Topology-Agnostic Networks-on-Chip
ACM Transactions on Design Automation of Electronic Systems (TODAES), Volume 24, Issue 2Article No.: 17, Pages 1–29https://doi.org/10.1145/3291532High--performance multiprocessor SoCs used in practice require a complex network-on-chip (NoC) as communication architecture, and the channels therein often suffer from various manufacturing defects. Such physical defects cause a multitude of system-...
- research-articleNovember 2016
DReAM: An Approach to Estimate per-Task DRAM Energy in Multicore Systems
ACM Transactions on Design Automation of Electronic Systems (TODAES), Volume 22, Issue 1Article No.: 16, Pages 1–26https://doi.org/10.1145/2939370Accurate per-task energy estimation in multicore systems would allow performing per-task energy-aware task scheduling and energy-aware billing in data centers, among other applications. Per-task energy estimation is challenged by the interaction between ...
- research-articleJune 2015
Least Upper Delay Bound for VBR Flows in Networks-on-Chip with Virtual Channels
ACM Transactions on Design Automation of Electronic Systems (TODAES), Volume 20, Issue 3Article No.: 35, Pages 1–33https://doi.org/10.1145/2733374Real-time applications such as multimedia and gaming require stringent performance guarantees, usually enforced by a tight upper bound on the maximum end-to-end delay. For FIFO multiplexed on-chip packet switched networks we consider worst-case delay ...
- research-articleJune 2014
Power Modeling for GPU Architectures Using McPAT
ACM Transactions on Design Automation of Electronic Systems (TODAES), Volume 19, Issue 3Article No.: 26, Pages 1–24https://doi.org/10.1145/2611758Graphics Processing Units (GPUs) are very popular for both graphics and general-purpose applications. Since GPUs operate many processing units and manage multiple levels of memory hierarchy, they consume a significant amount of power. Although several ...
- research-articleJune 2014
SPMCloud: Towards the Single-Chip Embedded ScratchPad Memory-Based Storage Cloud
ACM Transactions on Design Automation of Electronic Systems (TODAES), Volume 19, Issue 3Article No.: 22, Pages 1–45https://doi.org/10.1145/2611755The era of cloud computing on-a-chip is enabled by the aggressive move towards many-core platforms and the rapid adoption of Network-on-Chips. As a result, there is a need for large-scale distributed on-chip shared memories that are reliable, low power, ...
- research-articleOctober 2013
Enabling energy efficient reliability in embedded systems through smart cache cleaning
ACM Transactions on Design Automation of Electronic Systems (TODAES), Volume 18, Issue 4Article No.: 53, Pages 1–25https://doi.org/10.1145/2505012Incessant and rapid technology scaling has brought us to a point where today's, and future transistors are susceptible to transient errors induced by energy carrying particles, called soft errors. Within a processor, the sheer size and nature of data in ...
- research-articleApril 2013
Resource-aware architectures for adaptive particle filter based visual target tracking
ACM Transactions on Design Automation of Electronic Systems (TODAES), Volume 18, Issue 2Article No.: 22, Pages 1–27https://doi.org/10.1145/2442087.2442093There are a growing number of visual tracking applications now being envisioned for mobile devices. However, since computer vision algorithms such as particle filtering have large computational demands, they can result in high energy consumption and ...
- research-articleDecember 2009
Spatial locality exploitation for runtime reordering of JPEG2000 wavelet data layouts
- Bert Geelen,
- Vissarion Ferentinos,
- Francky Catthoor,
- Gauthier Lafruit,
- Diederik Verkest,
- Rudy Lauwereins,
- Thanos Stouraitis
ACM Transactions on Design Automation of Electronic Systems (TODAES), Volume 15, Issue 1Article No.: 8, Pages 1–6https://doi.org/10.1145/1640457.1640465Exploitation of spatial locality is essential for memories to increase the access bandwidth and to reduce the access-related latency and energy per word. Spatial locality exploitation of a kernel can be improved by modifying placement of data in memory, ...
- research-articleApril 2009
Battery voltage modeling for portable systems
ACM Transactions on Design Automation of Electronic Systems (TODAES), Volume 14, Issue 2Article No.: 29, Pages 1–36https://doi.org/10.1145/1497561.1497572Limited battery life imposes stringent constraints on the operation of battery-powered portable systems. During battery discharge, the battery voltage decreases, until a certain cutoff value is reached, marking the end of battery life. The amount of ...
- articleFebruary 2007
System-level performance/power analysis for platform-based design of multimedia applications
ACM Transactions on Design Automation of Electronic Systems (TODAES), Volume 12, Issue 1Article No.: 2, Pages 1–29https://doi.org/10.1145/1188275.1188277The objective of this article is to introduce the use of Stochastic Automata Networks (SANs) as an effective formalism for application-architecture modeling in system-level average-case analysis for platform-based design. By platform, we mean a family ...
- articleJune 2004
Computation and communication refinement for multiprocessor SoC design: A system-level perspective
ACM Transactions on Design Automation of Electronic Systems (TODAES), Volume 11, Issue 3Pages 564–592https://doi.org/10.1145/1142980.1142983Continuous advancements in semiconductor technology enable the design of complex systems-on-chips (SoCs) composed of tens or hundreds of IP cores. At the same time, the applications that need to run on such platforms have become increasingly complex and ...