Recent progress in the area of global routing has been remarkable; yet, in many ways, the classical formulation has yet to catch up with the demands imposed by modern physical synthesis flows. In this work, we visit (and revisit) the topic of global ...

Current logic synthesis techniques are ineffective for arithmetic circuits. They perform poorly for XOR-dominated circuits, and those with a high fan-in dependency between inputs and outputs. Many optimizers, therefore employ libraries of hand-optimized ...

During the IC design process, functional specifications are often modified late in the design cycle, after placement and routing are completed. However, designers are left either to manually process such modifications by hand or to restart the design ...

Boolean relations are an important tool in system synthesis and verification to characterize solutions to a set of Boolean constraints. For physical realization as hardware, a deterministic function often has to be extracted from a relation. Prior ...

Passivity is an important property for a macro-model generated from measured or simulated data. Existence of purely imaginary eigenvalues of a Hamiltonian matrix provides useful information in assessing and correcting the passivity of a system. Since ...

A generalized Hamiltonian method (GHM) is proposed for passivity test of descriptor systems (DSs) which describe impedance or admittance input-output responses. GHM can test passivity of DSs with any system index without minimal realization. This ...

Synthesis of multi-GigaHertz radio frequency circuits brings together difficult challenges related to simulation, extraction and multidimensional space search. The standard approach of mapping all electromagnetic parasitics into parametric RLC models ...

With the adoption of ultra regular fabric paradigms for controlling design printability at the 22nm node and beyond, there is an emerging need for a layout-driven, pattern-based parasitic extraction of alternative fabric layouts. In this paper, we ...

Decoupling capacitance (decap) is an efficient way to reduce transient noise in on-chip power supply networks. However, excessive decap may cause more leakage power, chip resource waste, and even lead to more design iterations. In this paper, we present ...

Joint design time and post-silicon optimization for analog circuits has been an open problem in literature because of the complex nature of analog circuit modeling and optimization. In this paper we formulate the co-optimization problem for digitally ...

Brute-force simulation approaches to estimating serial-link bit-error rates (BERs) become computationally intractable for the case when BERs are low and the interconnect electrical response is slow enough to generate intersymbol interference that spans ...

Electronic design automation (EDA) tools have facilitated the design of ever more complex integrated circuits each year. Synthetic biology would also benefit from the development of genetic design automation (GDA) tools. Existing GDA tools require ...

Through-Silicon-Via (TSV) is the enabling technology for the fine-grained 3D integration of multiple dies into a single stack. These TSVs occupy non-negligible silicon area because of their sheer size. This significant silicon area occupied by the TSVs ...

Excessive supply voltage drops in a circuit may lead to significant circuit performance degradation and even malfunction. To handle this problem, existing power delivery aware placement algorithms model voltage drops as an optimization objective. We ...

Accurate and fast estimation of VLSI interconnect thermal profiles has become critically important to estimate their impact on circuit/system performance and reliability, which is necessary for reducing product development time and achieving first-pass ...

Existing thermal management systems for microprocessors assume that the thermal resistance of the heat-sink is constant and that the objective of the cooling system is simply to avoid thermal emergencies. But in fact the thermal resistance of the usual ...

SRAM cell design is driven by the need to satisfy static noise margin, write margin and read current margin (RCM) over all cells in the array in an energy-efficient manner. These constraints determine both the minimum cell size and supply voltage. RCM ...

Static Random Access Memories (SRAMs) are key components of modern VLSI designs and a major bottleneck to technology scaling as they use the smallest size devices with high sensitivity to manufacturing details. Analysis performed at the "schematic" ...

In this paper, an adaptive sampling method is proposed for the statistical SRAM cell analysis. The method is composed of two components. One part is the adaptive sampler that manipulates an alternative sampling distribution iteratively to minimize the ...

Design rules have been the primary contract between technology and design and are likely to remain so to preserve abstractions and productivity. While current approaches for defining design rules are largely unsystematic and empirical in nature, this ...