In this paper, we propose dual-channel access mechanism to design cost-effective NoC based on 2D-mesh topology. Compared with traditional single-channel access mechanism, our scheme greatly increases the throughput and cuts down the average latency with ...

In this paper we examine a latency insensitive network composed of very fast and simple circuits that connects SoC cores that are also latency insensitive, de-synchronized, or asynchronous. These types of cores provide native flow control that is ...

Through low-level simulation and analysis, we find that the virtual channel allocator (VA) consumes large area and power while it is not critical in the performances of a NoC. Thus, it is possible to reduce the costs of VA with only a small penalty in ...

Network-on-chip has been proposed as an alternative to bus-based system to achieve high performance and scalability. The topology of on-chip interconnect plays a crucial role in System on chip performance, energy, and area requirements. In this paper, ...

Our characterization of a suite of commercial and scientific workloads on a 16-core cache-coherent chip multiprocessor (CMP) shows that overall system performance is sensitive to on-chip communication latency, and can degrade by 20% or more due to long ...

This paper introduces a cost-effective technique to deal with CMP coherence protocol requirements from the interconnection network point of view. A mechanism is presented to avoid the end-to-end deadlock that arises from the dependency chains created at ...

Chip multiprocessors (CMPs) combine increasingly many general-purpose processor cores on a single chip. These cores run several tasks with unpredictable communication needs, resulting in uncertain and often-changing traffic patterns. This ...

This paper presents a physical implementation of the DSPIN network-on-chip in the FAUST architecture. FAUST is a stream-oriented multi-application SoC platform for telecommunications addressing IEEE 802.11a and MC-CDMA standards. The original ...

In this paper, a low power joint bus and error correction coding is proposed to provide reliable and energy-efficient interconnection for network-on-chip (NoC) in nano-scale technology. The proposed self-corrected “green” (low power) coding scheme is ...

We propose that networks on chip (NOC) are hardwired in Field-Programmable Gate Arrays (FPGA). Although some area of the FPGA then has a fixed function, this loss of flexibility is outweighed by the following benefits. First, implementation cost is much ...

Our investigation into Networks-on-Chip for Field-Programmable Gate Arrays (FPGAs) indicates that fine-grain time-division multiplexing over configurable wires can significantly reduce the number of interconnects needed and therefore reduce chip area. ...

In this paper, we introduce the use of slow-silent virtual channels to reduce the switching power of on-chip networks while keeping the leakage power small. Adding virtual channels to a network improves the throughput until each link bandwidth is ...

We present a methodology to debug a SOC by concentrating on its communication. Our extended communication model includes a) multiple signal groups per interface protocol at each IP port, b) the handshakes per signal group (e.g. for command), and c) the ...