This paper presents a novel run-time dynamic voltage scaling scheme for low-power real-time systems. It employs software feedback control of supply voltage, which is applicable to off-the-shelf processors. It avoids interface problems from variable ...

In this paper we describe an area efficient power minimization scheme. “Control Generated Clocking” that saves significant amounts of power in datapath registers and clock drivers of sequential circuits. Power savings are achieved by making simple ...

High-performance memory buses consume large energy as they include termination networks, BiCMOS and/or open-drain output. This paper introduces power reduction techniques for memory systems deliberating on burst-mode transfers over the high-speed bus ...

Joint module selection and retiming is a powerful technique to optimize the implementation cost and the speed of a circuit specified using a synchronous data-flow graph (DFG). In implementing high-speed circuits, the use of carry-save signal ...

In this paper, we propose a technique to implement communication protocols as hardware circuits using a model of concurrent EFSMs with multi-way synchronization. Since use of multi-way synchronization enables simple and comprehensible specifications of ...

A method for high level synthesis-for-testability of controller-datapath pairs that use gated clocks is developed. It uses a register allocation technique that improves the observability of the controller through the datapath, and takes advantage of the ...

This paper develops the noise-counterparts to familiar delay formulas like Elmore or PRIMO. By matching the first few moments of the network's transfer impedance, we obtain efficient and accurate predictions for maximum noise between two capacitively ...

Signal integrity analysis has become imperative for high-speed designs. In this paper, we present a new technique to advance Krylov-space based passive model-reduction algorithms to include lossy coupled transmission lines described by Telegrapher's ...

In this chapter, we present a general methodology for the design of custom system-on-chip communication architectures. Our technique is based on the addition of a layer of circuitry, called the Communication Architecture Tuner (CAT), around any existing ...

Substrate noise caused by large digital circuits will degrade the performance of analog circuits located on the same substrate. To simulate this performance degradation, the total amount of generated substrate noise must be known. Simulating substrate ...

The explosion of the telecommunications market requires miniaturization and cost-effective realization of the front-ends of transceivers for digital telecommunications. New architectures must therefore be simulated at high level. Current methodologies ...

A main advantage of control composition with modal processes [4] is the enhanced retargetability of the composed behavior over a wide variety of target architectures. Unlike previous component models that hardwire the coordination behavior either ...

We present a programming interface called YAPI to model signal processing applications as process networks. The purpose of YAPI is to enable the reuse of signal processing applications and the mapping of signal processing applications onto heterogeneous ...

High-level development tools for digital signal processors (DSPs) remain unable to extract optimal performance from them without the designer's in-depth knowledge of the architecture. In this paper we describe our approach to Retargetable Estimation and ...

Based on the new concept of crosstalk immunity set (CIS), procedures to minimize capacitive cross-coupling effects are developed for domino logic circuit. The nets in a crosstalk immunity set are free from crosstalk effects for any combination of input ...

This paper presents a method for general reduced order analysis of linear circuits with a large number of independent sources. This type of circuit is used to model the power grid in power supply noise analysis for example. The large size of the linear ...

A dynamic noise model is developed and applied to analyze the noise immunity of precharge-evaluate circuits. Considering that the primary source of noise-injection in the circuit is cross-talk, a simple metric represented as voltage-time product can be ...

In this paper, we extend transistor-level static noise analysis tools to consider the unique features of partially-depleted silicon-on-insulator (PD-SOI) technology: floating-body-induced threshold voltage variations and parasitic bipolar leakage ...

We describe the first iteration of a comprehensive model with which we can investigate the practical limits on optical bus bandwidth and number of bus processing modules for given signal power. The selection algorithm will ultimately allow programmable ...

This paper describes a novel formal verification approach for equivalence checking of small, assembly-language routines for digital signal processors (DSP). By combining control-flow analysis, symbolic simulation, automatic decision procedures, and some ...