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A methodology for efficient high-level dataflow simulation of mixed-signal front-ends of digital telecom transceivers

Published: 01 June 2000 Publication History

Abstract

The explosion of the telecommunications market requires miniaturization and cost-effective realization of the front-ends of transceivers for digital telecommunications. New architectures must therefore be simulated at high level. Current methodologies and corresponding tools suffer from common drawbacks, such as lower accuracy, slow simulation speed, etc. A new methodology has been developped for the efficient simulation, at the architectural level, of mixed-signal front-ends of digital telecom transceivers. The efficient execution is obtained using a multi-rate, multi-carrier signal representation together with a dataflow simulation scheme which switches dynamically towards the most efficient signal processing technique available. An implementation of this methodology shows both excellent runtimes and a high accuracy.

References

[1]
Communication toolbox of MATLAB/ SIMULINK, http ://www.mathworks.com/products/communications/.
[2]
I. Vassiliou and A. Sangiovanni-Vincentelli, "A frequencydomain, Volterra series-based behavioral simulation tool for RF systems," Proc. IEEE Custom Integrated Circuits Conference, pp. 21-24, 1999.
[3]
Jeruchim, Balaban and Shanmugan, "Simulation of Communication Systems," Plenum, 1992.
[4]
COSSAP of Synopsis, http://www.synopsis.com/products/dsp/cossap_ds.html.
[5]
SPW of Cadence, http://www.cadence.com/software/cierto/
[6]
A. Rofougaran et al., "A 1 GHz CMOS RF front-end IC for a direct-conversion wireless transceiver," IEEE J. Solid- State Circuits, Vol. 31, pp. 880-889, July 1996.
[7]
J. Crols and M. Steyaert, "A single-chip 900 MHz CMOS receiver front-end with a high-performance low-IF topology," IEEE J. Solid-State Circuits, Vol. 30, pp. 1483- 1492, Dec. 1995.
[8]
J. Rudell et al., "A 1.9-GHz wide-band IF double conversion CMOS receiver for cordless telephone applications," IEEE J. Solid-State Circuits, Vol. 32, pp. 2071-2088, Dec. 1997.
[9]
J. Chen, D. Feng, J. Philips and K. Kundert, "Simulation and modeling of intermodulation distortion in communication circuits," Proc. IEEE Custom Integrated Circuits Conference, pp. 5-8, 1999.
[10]
P. Schaumont et a/., "A programming environment for the design of complex high speed ASICs", Proceedings of DAC, pp. 315-320, June 1998.
[11]
J.L. Pino and K. Kalbasi, "Cosimulating synchronous DSP applications with analog RF circuits," Proc. 32nd Annual Asilomar Conference on Signals, Systems, and Computers, Nov. 1998.
[12]
HP-ADS of Hewlett-Packard, http ://www.tm.agilent.com/tmo/hpeesof/products/ads/adsovi ew.html.
[13]
E. Ngoya and R. Larchev6que, "Envelop transient analysis: a new method for the transient and steady state analysis of microwave communication circuits and systems," Proc. IEEE MTT-S, pp. 1365-1368, 1996.
[14]
P. Wambacq and W. Sansen, "Distortion analysis of analog integrated circuits," Kluwer Academic Publishers, 1998.
[15]
R. Sea, "An algebraic formula for amplitudes of intermodulation products involving an arbitrary number of frequencies," Proc. IEEE, pp. 1388-1389, Aug. 1968.
[16]
Ptolemy of the University of Berkeley, http://ptolemy.eecs.berkeley.edu.

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cover image ACM Conferences
DAC '00: Proceedings of the 37th Annual Design Automation Conference
June 2000
819 pages
ISBN:1581131879
DOI:10.1145/337292
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 01 June 2000

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