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- ArticleApril 2006
Session Abstract
VTS '06: Proceedings of the 24th IEEE VLSI Test SymposiumPages 150–151https://doi.org/10.1109/VTS.2006.76According to the Moore's Law, the number of transistors per integrated circuit doubles every 24 months, and it has been the guiding principle for the silicon semiconductor industry for over 30 years. The sustaining of the Moore's Law, however, requires ...
- ArticleJanuary 2004
Infrastructures for Education, Research and Industry in Microelectronics - A review
Infrastructures to provide access to custom integratedhardware manufacturing facilities are importantbecause they allow Students and Researchers to accessprofessional facilities at a reasonable cost, and theyallow Companies to access small volume ...
- ArticleJanuary 2004
On-chip testing of embedded transducers
System-on-Chip (SoC) technologies are evolving towardsthe integration of highly heterogeneous devices, includinghardware of a different nature, such as digital, analogueand mixed-signal, together with software components.Embedding transducers, as ...
- research-articleApril 2000
Design of self-checking fully differential circuits and boards
IEEE Transactions on Very Large Scale Integration (VLSI) Systems (ITVL), Volume 8, Issue 2Pages 113–128https://doi.org/10.1109/92.831432A design methodology for on-line testing analog linear fully differential (FD) circuits is presented in this work. The test strategy is based on concurrently monitoring via an analog checker the common mode (Chi) at the inputs of all amplifiers, The ...
- ArticleMarch 2000
Towards design and validation of mixed-technology SOCs
GLSVLSI '00: Proceedings of the 10th Great Lakes symposium on VLSIPages 29–33https://doi.org/10.1145/330855.330950This paper illustrates an approach to design and validation of heterogeneous systems. The emphasis is placed on devices which incorporate MEMS parts in either a single mixed-technology (CMOS + micromachining) SOC device, or alternatively as a hybrid ...
- chapterSeptember 1998
Thermal monitoring of self-checking systems
On-line testing for VLSISeptember 1998, Pages 81–92 - articleFebruary 1998
Thermal Monitoring of Self-Checking Systems
Journal of Electronic Testing: Theory and Applications (JELT), Volume 12, Issue 1-2Pages 81–92https://doi.org/10.1023/A:1008233907036With the increasing power density in integrated systems resulting from scaling down, the occurrence of field failures due to overheating has considerably increased. Faulty operation can be prevented by on-line temperature monitoring. This paper deals with ...
- ArticleApril 1997
Integrating on-chip temperature sensors into DfT schemes and BIST architectures
The continuously increasing power densities in integrated circuits necessitated the introduction of DfTT (Design for Thermal Testability) design methodology to prevent overheating effects. Newly developed CMOS temperature sensors enable the application ...
- research-articleMay 1989
Random Pattern Testing Versus Deterministic Testing of RAMs
IEEE Transactions on Computers (ITCO), Volume 38, Issue 5Pages 637–650https://doi.org/10.1109/12.24267The number of (random) patterns required for random testing of RAMs (random-access memories), when classical fault models including pattern-sensitive faults are considered is determined. Markov chains are a powerful tool for this purpose. Single faults ...
- research-articleJune 1988
Definition and Design of Strongly Language Disjoint Checkers
IEEE Transactions on Computers (ITCO), Volume 37, Issue 6Pages 745–748https://doi.org/10.1109/12.2215Strongly language-disjoint (SLD) checkers are to sequential systems what strongly code-disjoint checkers are to combinatorial systems. SLD checkers are the largest class of checkers with which a functional system can achieve the totally self-checking ...
- articleApril 1988
An integrated debugging system based on E-beam test
Microelectronic Engineering (MCEE), Volume 7, Issue 2-4Pages 275–282https://doi.org/10.1016/S0167-9317(87)80022-9A data processing system, as part of a whole integrated test system for debugging VLSI circuits using a scanning electron microscope is described here. A link between a CALMA description and the S.E.M. images of a circuit is particularly reported. This ...
- ArticleJuly 1986
Principles of the SYCO compiler
The SYCO system is a silicon compiler for VLSI circuits specified by algorithms. The SYCO system starts from an algorithmic description and produces a microprocessor-like circuit that realizes the algorithm. It uses a target architecture based on a ...
