On-Line Testing for VLSI—A Compendium of Approaches
This paper presents an overview of a comprehensive collection of on-line testing techniques for VLSI. Such techniques are for instance: self-checking design, allowing high quality concurrent checking by means of hardware cost drastically lower than ...
On-Line Fault Monitoring
Sequoia‘s fault-tolerant computers were designed subject to some rather rigid constraints: No single hardware malfunction can generate an undetected error; an integrated circuit is a “black box” that can fail in arbitrary ways, affecting an arbitrary ...
Efficient Totally Self-Checking Shifter Design
Self-checking designs will gain increasing interest in industrial applications if they satisfy the following requirements: high fault coverage, reduced hardware cost and reduced design effort. This work is aimed to reach these requirements for the design ...
A New Design Method for Self-Checking Unidirectional Combinational Circuits
In this paper, a new method for the design of unidirectional combinational circuits is proposed. Carefully selected non-unidirectional gates of the original circuit are duplicated such that every single gate fault can only be propagated to the circuit ...
Concurrent Delay Testing in Totally Self-Checking Systems
Prompt detection of even small delay faults, sometimes before causing critical paths to fail, gains importance since stricter test quality requirements for high performance and high density VLSI circuits have to be satisfied in critical applications. ...
Design of Self-Testing Checkers for m-out-of-n Codes Using Parallel Counters
This paper extends the design method of self-testing checkers (STCs) for some m-out-of-n (m/n) codes, proposed recently in IEEE Trans. Comput., 1995 by Dimakopoulos et al. The checkers are built using a pair of parallel counters (composed of full-adders and ...
Self-Testing Embedded Two-Rail Checkers
This paper presents a new simple and straightforward method for designing Completely Testable Embedded (CTE) parity trees, and Self-Testing Embedded (STE) two-rail checkers. In the design of CTE parity trees the two inputs XOR gate has been used as the ...
Thermal Monitoring of Self-Checking Systems
With the increasing power density in integrated systems resulting from scaling down, the occurrence of field failures due to overheating has considerably increased. Faulty operation can be prevented by on-line temperature monitoring. This paper deals with ...
Integrated Temperature Sensors for On-Line Thermal Monitoring of Microelectronic Structures
Built-in temperature sensors increase the system reliability by predicting eventual faults caused by excessive chip temperatures. In this paper, simple and efficient built-in temperature sensors for the on-line thermal monitoring of microelectronics ...
Clocked Dosimeter Compatible with Digital CMOS Technology
We present two versions of a radiation dosimeter, they are CMOS circuits built around a PMOSFET radiation sensor, compatible with standard technology. These dosimeters are intended to be used as built-in sensors in integrated circuits to signal misfunction ...
Scalable Test Generators for High-Speed Datapath Circuits
This paper explores the design of efficient test sets and test-pattern generators for on-line BIST. The target applications are high-performance, scalable datapath circuits for which fast and complete fault coverage is required. Because of the presence of ...
Mixed-Mode BIST Using Embedded Processors
In complex systems, embedded processors may be used to run software routines for test pattern generation and response evaluation. For system components which are not completely random pattern testable, the test programs have to generate deterministic ...
A Bist Scheme for Non-Volatile Memories
A new BIST scheme for on-chip testing of non-volatile memories and based on signature analysis is presented. The signature of the whole memory, whose content can be changed selectively by the user, is dynamically self-learned by the memory and it is saved ...
On-Line Fault Resilience Through Gracefully Degradable ASICs
We present two novel reconfiguration schemes, L/U reconfiguration and its generalization, band reconfiguration, to achieve graceful degradation for general microarchitecture datapaths. Upon detection of a datapath fault, hardware and algorithmic ...
Delivering Dependable Telecommunication Services Using Off-the-Shelf System Components
For decades, traditional telecommunication systems have reliably delivered telephony services using expensive equipment and software. In spite of large R&D expenses, the end customer costs remained low due to the amortization of the equipment over a large ...
