article

Self-Testing Embedded Two-Rail Checkers

Author:

Dimitris NikolosAuthors Info & Claims

Journal of Electronic Testing: Theory and Applications, Volume 12, Issue 1-2

Pages 69 - 79

https://doi.org/10.1023/A:1008281822966

Published: 01 February 1998 Publication History

Abstract

This paper presents a new simple and straightforward method for designing Completely Testable Embedded (CTE) parity trees, and Self-Testing Embedded (STE) two-rail checkers. In the design of CTE parity trees the two inputs XOR gate has been used as the building block. In the case of STE two-rail checkers with n input pairs the building block is the two-rail checker with 2 input pairs. During normal, fault free, operation each XOR gate receives all possible input vectors, while each two-rail checker with 2 input pairs receives all possible code input vectors. The great advantage of the proposed method is that it is the only one that gives in a simple and straightforward way an optimal CTE/STE tree realization with respect to the hardware (number of blocks) and the speed (number of block levels). Designing the two input two-rail checker as proposed by Lo in IEEE J. of Solid-State Circuits, 1993, we get optimal STE two-rail checkers taking into account realistic faults.

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Cited By

Omana MRossi DMetra C(2005)Low Cost and High Speed Embedded Two-Rail Code CheckerIEEE Transactions on Computers10.1109/TC.2005.3054:2(153-164)Online publication date: 1-Feb-2005
https://dl.acm.org/doi/10.1109/TC.2005.30
Piestrak S(2002)Design Method of a Class of Embedded Combinational Self-Testing Checkers for Two-Rail CodesIEEE Transactions on Computers10.1109/12.98001051:2(229-234)Online publication date: 1-Feb-2002
https://dl.acm.org/doi/10.1109/12.980010

Index Terms

Self-Testing Embedded Two-Rail Checkers

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Information

Published In

cover image Journal of Electronic Testing: Theory and Applications

Journal of Electronic Testing: Theory and Applications Volume 12, Issue 1-2

Special issue on On-line testing

Feb./April 1998

146 pages

ISSN:0923-8174

Editors:
Vishwani Agrawal
Bell Labs, Lucent Technologies
,
Michael Nicolaidis
TIMA, Grenoble, France
,
Yervant Zorian
LogicVision, San Jose, CA
,
Dhiraj K. Pradhan
Texas A&M Univ., College Station, TX

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Copyright © Copyright © 1998 Kluwer Academic Publishers.

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Kluwer Academic Publishers

United States

Publication History

Published: 01 February 1998

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Cited By

Omana MRossi DMetra C(2005)Low Cost and High Speed Embedded Two-Rail Code CheckerIEEE Transactions on Computers10.1109/TC.2005.3054:2(153-164)Online publication date: 1-Feb-2005
https://dl.acm.org/doi/10.1109/TC.2005.30
Piestrak S(2002)Design Method of a Class of Embedded Combinational Self-Testing Checkers for Two-Rail CodesIEEE Transactions on Computers10.1109/12.98001051:2(229-234)Online publication date: 1-Feb-2002
https://dl.acm.org/doi/10.1109/12.980010

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