research-article

Optimal Self-Testing Embedded Parity Checkers

Author:

Dimitris NikolosAuthors Info & Claims

IEEE Transactions on Computers, Volume 47, Issue 3

Pages 313 - 321

https://doi.org/10.1109/12.660167

Published: 01 March 1998 Publication History

Abstract

This paper presents a new simple and straightforward method for designing Self-Testing Embedded (STE) parity checkers. The building block is the two-input XOR gate. During normal, fault-free operation, each XOR gate receives all possible input vectors. The great advantage of the proposed method is that it is the only one that gives, in a simple and straightforward way, optimal STE realizations with respect to the cost (number of XOR gates) and the speed (number of XOR gate levels).

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Cited By

Oikonomakos PZwolinski M(2006)On the Design of Self-Checking Controllers with Datapath InteractionsIEEE Transactions on Computers10.1109/TC.2006.18555:11(1423-1434)Online publication date: 1-Nov-2006
https://dl.acm.org/doi/10.1109/TC.2006.185
Tarnick S(2005)Single- and Double-Output Embedded Checker Architectures for Systematic Unordered Codes"Journal of Electronic Testing: Theory and Applications10.1007/s10836-005-0973-y21:4(391-404)Online publication date: 1-Aug-2005
https://dl.acm.org/doi/10.1007/s10836-005-0973-y
Lo HLin HChen CLiu JLiu C(2003)Built-in Test with Modified-Booth High-Speed Pipelined Multipliers and DividersJournal of Electronic Testing: Theory and Applications10.1023/A:102379281252119:3(245-269)Online publication date: 1-Jun-2003
https://dl.acm.org/doi/10.1023/A%3A1023792812521
Show More Cited By

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Optimal Self-Testing Embedded Parity Checkers

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Published In

cover image IEEE Transactions on Computers

IEEE Transactions on Computers Volume 47, Issue 3

March 1998

97 pages

ISSN:0018-9340

Editor:
Jane W. S. Liu
Univ. of Illinois

Issue’s Table of Contents

Copyright © Copyright © 1998 IEEE. All Rights Reserved.

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IEEE Computer Society

United States

Publication History

Published: 01 March 1998

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Cited By

Oikonomakos PZwolinski M(2006)On the Design of Self-Checking Controllers with Datapath InteractionsIEEE Transactions on Computers10.1109/TC.2006.18555:11(1423-1434)Online publication date: 1-Nov-2006
https://dl.acm.org/doi/10.1109/TC.2006.185
Tarnick S(2005)Single- and Double-Output Embedded Checker Architectures for Systematic Unordered Codes"Journal of Electronic Testing: Theory and Applications10.1007/s10836-005-0973-y21:4(391-404)Online publication date: 1-Aug-2005
https://dl.acm.org/doi/10.1007/s10836-005-0973-y
Lo HLin HChen CLiu JLiu C(2003)Built-in Test with Modified-Booth High-Speed Pipelined Multipliers and DividersJournal of Electronic Testing: Theory and Applications10.1023/A:102379281252119:3(245-269)Online publication date: 1-Jun-2003
https://dl.acm.org/doi/10.1023/A%3A1023792812521
Stroele ATarnick S(2000)Embedded Checker Architectures for Cyclic and Low-Cost Arithmetic CodesJournal of Electronic Testing: Theory and Applications10.1023/A:100831800284616:4(355-367)Online publication date: 1-Aug-2000
https://dl.acm.org/doi/10.1023/A%3A1008318002846
Stroele ATarnick S(1999)Programmable Embedded Self-Testing Checkers for All-Unidirectional Error-Detecting CodesProceedings of the 1999 17TH IEEE VLSI Test Symposium10.5555/832299.836497Online publication date: 26-Apr-1999
https://dl.acm.org/doi/10.5555/832299.836497
Tarnick SStroele A(1998)Embedded self-testing checkers for low-cost arithmetic codesProceedings of the 1998 IEEE International Test Conference10.5555/648020.761112(514-523)Online publication date: 18-Oct-1998
https://dl.acm.org/doi/10.5555/648020.761112

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