Optimal Circuits for Parallel Multipliers
We present new design and analysis techniques for the synthesis of parallel multiplier circuits that have smaller predicted delay than the best current multipliers. In [4], Oklobdzija et al. suggested a new approach, the Three-Dimensional Method (TDM), ...
Optimal Elections in Faulty Loop Networks and Applications
Loop networks (or Hamiltonian circulant graphs) are a popular class of fault-tolerant network topologies which include rings and complete graphs. For this class, the fundamental problem of Leader Election has been extensively studied, assuming either a ...
Optimal Diagnosis of Heterogeneous Systems with Random Faults
We consider the problem of fault diagnosis in multiprocessor systems. Processors perform tests on one another; fault-free testers correctly identify the fault status of tested processors, while faulty testers can give arbitrary test results. Processors ...
Random Pattern Testability of Memory Control Logic
This paper analyzes the random pattern testability of faults in the control logic of an embedded memory. We show how to compute exposure probabilities of these faults using mostly signal probability computations. We also show that the hardest memory ...
Optimal Self-Testing Embedded Parity Checkers
This paper presents a new simple and straightforward method for designing Self-Testing Embedded (STE) parity checkers. The building block is the two-input XOR gate. During normal, fault-free operation, each XOR gate receives all possible input vectors. ...
Load Balancing Problems for Multiclass Jobs in Distributed/Parallel Computer Systems
Load balancing problems for multiclass jobs in distributed/parallel computer systems with general network configurations are considered. We construct a general model of such a distributed/parallel computer system. The system consists of heterogeneous ...
A Simplified Architecture for Modulo (2n + 1) Multiplication
The modulo (2n + 1) multiplication is widely used in the computation of convolutions and in RNS arithmetic and, thus, it is important to reduce the calculation delay. This paper presents a concept of a modulo (2n + 1) carry save adder (MCSA) and uses ...
Logic Testing of Bridging Faults in CMOS Integrated Circuits
We describe a system for simulating and generating accurate tests for bridging faults in CMOS ICs. After introducing the Primitive Bridge Function, a characteristic function describing the behavior of a bridging fault, we present the Test Guarantee ...
A VLSI Architecture for Approximate Tree Matching
The distance between two labeled ordered trees, and β, is the minimum cost sequence of editing operations (insertions, deletions, and substitutions) needed to transform into β such that the predecessor-descendant relation between nodes and the ordering ...
Low-Complexity Bit-Parallel Canonical and Normal Basis Multipliers for a Class of Finite Fields
We present a new low-complexity bit-parallel canonical basis multiplier for the field GF(2m) generated by an all-one-polynomial. The proposed canonical basis multiplier requires m2$-$ 1 XOR gates and m2 AND gates. We also extend this canonical basis ...
High Performance Fault-Tolerant Digital Neural Networks
Efficient implementation of neural networks requires high-performance architectures, while VLSI realization for mission-critical applications must include fault tolerance. Contemporaneous solution of such problems has not yet been completely afforded in ...
Regular Sparse Crossbar Concentrators
A bipartite concentrator is a single stage sparse crossbar switching device that can connect any m of its n m inputs to its m outputs, possibly without the ability to distinguish their order. Fat-and-slim crossbars were introduced recently to show that ...
