research-article

Design Techniques for Testable Embedded Error Checkers

Author:

E. J. McCluskeyAuthors Info & Claims

Computer, Volume 23, Issue 7

Pages 84 - 88

https://doi.org/10.1109/2.56855

Published: 01 July 1990 Publication History

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Abstract

Design techniques to ensure the testability of embedded checkers that cannot be tested by scan-path bistables are presented. The discussion covers: types of error detectors; parity checkers and self-testing circuits; two-rail checkers; M-out-of-N checkers; and equality checkers. The techniques outline guarantee single stuck fault testability.

References

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7. J. Khakbaz and E.J. McCluskey, "Self-Testing Embedded Code Checkers," Digest Compcon Spring 83, Computer Society Press, Los Alamitos, Calif., Order No. 458 (microfiche only), pp. 452-457.

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Cited By

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Almukhaizim SBunian SSinanoglu O(2013)Reconfigurable Concurrent Error Detection Adaptive to Dynamicity of Power ConstraintsJournal of Electronic Testing: Theory and Applications10.1007/s10836-012-5347-729:1(73-86)Online publication date: 1-Feb-2013
https://dl.acm.org/doi/10.1007/s10836-012-5347-7
Dimitrakopoulos GKalligeros E(2012)Low-cost fault-tolerant switch allocator for network-on-chip routersProceedings of the 2012 Interconnection Network Architecture: On-Chip, Multi-Chip Workshop10.1145/2107763.2107770(25-28)Online publication date: 25-Jan-2012
https://dl.acm.org/doi/10.1145/2107763.2107770
Mitra SBrelsford KSanda PDe Micheli GAl-Hashimi BMueller WMacii E(2010)Cross-layer resilience challengesProceedings of the Conference on Design, Automation and Test in Europe10.5555/1870926.1871179(1029-1034)Online publication date: 8-Mar-2010
https://dl.acm.org/doi/10.5555/1870926.1871179
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Index Terms

Design Techniques for Testable Embedded Error Checkers
1. Hardware
  1. Hardware test
    1. Test-pattern generation and fault simulation
  2. Robustness
    1. Fault tolerance
      1. Error detection and error correction

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Published In

Computer Volume 23, Issue 7

July 1990

109 pages

ISSN:0018-9162

Editor:
Bruce D. Shriver
Univ. of Southwestern Louisiana, Lafayette

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IEEE Computer Society Press

Washington, DC, United States

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Published: 01 July 1990

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Almukhaizim SBunian SSinanoglu O(2013)Reconfigurable Concurrent Error Detection Adaptive to Dynamicity of Power ConstraintsJournal of Electronic Testing: Theory and Applications10.1007/s10836-012-5347-729:1(73-86)Online publication date: 1-Feb-2013
https://dl.acm.org/doi/10.1007/s10836-012-5347-7
Dimitrakopoulos GKalligeros E(2012)Low-cost fault-tolerant switch allocator for network-on-chip routersProceedings of the 2012 Interconnection Network Architecture: On-Chip, Multi-Chip Workshop10.1145/2107763.2107770(25-28)Online publication date: 25-Jan-2012
https://dl.acm.org/doi/10.1145/2107763.2107770
Mitra SBrelsford KSanda PDe Micheli GAl-Hashimi BMueller WMacii E(2010)Cross-layer resilience challengesProceedings of the Conference on Design, Automation and Test in Europe10.5555/1870926.1871179(1029-1034)Online publication date: 8-Mar-2010
https://dl.acm.org/doi/10.5555/1870926.1871179
Cardarilli GPontarelli SRe MSalsano A(2007)Concurrent error detection in Reed-Solomon encoders and decodersIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2007.89924115:7(842-846)Online publication date: 1-Jul-2007
https://dl.acm.org/doi/10.1109/TVLSI.2007.899241
Almukhaizim SMakris Y(2007)Concurrent Error Detection Methods for Asynchronous Burst-Mode MachinesIEEE Transactions on Computers10.1109/TC.2007.102556:6(785-798)Online publication date: 1-Jun-2007
https://dl.acm.org/doi/10.1109/TC.2007.1025
Zhang RJha NQu GIsmail YNarayanan VZhou H(2006)Threshold/majority logic synthesis and concurrent error detection targeting nanoelectronic implementationsProceedings of the 16th ACM Great Lakes symposium on VLSI10.1145/1127908.1127913(8-13)Online publication date: 30-Apr-2006
https://dl.acm.org/doi/10.1145/1127908.1127913
Nikolos D(1998)Self-Testing Embedded Two-Rail CheckersJournal of Electronic Testing: Theory and Applications10.1023/A:100828182296612:1-2(69-79)Online publication date: 1-Feb-1998
https://dl.acm.org/doi/10.1023/A%3A1008281822966

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Recommendations

Exact probabilistic analysis of error detection for parity checkers

Design of Embedded m-out-of-n Code Checkers Using Complete Parallel Counters

A Delay-Adjustable, Self-Testable Flip-Flop for Soft-Error Tolerability and Delay-Fault Testability

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