research-article

Fault Tolerance in VLSI Circuits

Authors:

Israel Koren,

Adit D. SinghAuthors Info & Claims

Computer, Volume 23, Issue 7

Pages 73 - 83

https://doi.org/10.1109/2.56854

Published: 01 July 1990 Publication History

Publisher Site

Abstract

The defects that can occur when manufacturing VLSI ICs and the faults that can result are described. Some commonly used restructuring techniques for avoiding defective components are discussed. Several defect-tolerant designs of memory ICs, logic ICs, and wafer-scale circuits are presented. Yield models for predicting the yield of chips with redundancy are introduced, and the optimal amount of redundancy is determined.

References

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Cited By

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Taher FCallenes-Sloan JSchafer B(2018)A machine learning based hard fault recuperation model for approximate hardware acceleratorsProceedings of the 55th Annual Design Automation Conference10.1145/3195970.3195974(1-6)Online publication date: 24-Jun-2018
https://dl.acm.org/doi/10.1145/3195970.3195974
Takanami IHorita TAkiba MTerauchi MKanno T(2016)A Built-in Self-repair Circuit for Restructuring Mesh-Connected Processor Arrays by Direct Spare ReplacementTransactions on Computational Science XXVII - Volume 957010.1007/978-3-662-50412-3_7(97-119)Online publication date: 1-Feb-2016
https://dl.acm.org/doi/10.1007/978-3-662-50412-3_7
Agarwal ACong JTagiku B(2013)The survivability of design-specific spare placement in FPGA architectures with high defect ratesACM Transactions on Design Automation of Electronic Systems10.1145/2442087.244210418:2(1-22)Online publication date: 11-Apr-2013
https://dl.acm.org/doi/10.1145/2442087.2442104
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Index Terms

Fault Tolerance in VLSI Circuits
1. Hardware

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Reviews

Reviewer: Albert Alkins Mullin

Modern VLSI chip technologies provide high circuit counts; enhance chip yield; and improve systems performance, effectiveness, reliability, maintainability, and speed. In seeking these desirable ends, manufacturers face a continual uphill battle against the adverse effects of random fabrication defects, no matter how good their manufacturing processes are. Applications of on-chip fault tolerance in the form of redundancy can reduce the problems of fabrication defects and thus enhance yield. Briefly, redundancy makes effective wafer-scale integrated circuits feasible. The authors' approach to yield enhancement adopts on-chip testing and reconfiguration capabilities. They carefully discuss yield modeling using Poisson statistics. Chip design for testability is automatically accommodated. As chips become larger (feature sizes are already approaching their physical minima) to meet the pressing needs of advanced robotics, process control, and artificial intelligence, the authors' defect-tolerance techniques will become increasingly more useful, if not routine.

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Information

Published In

Computer Volume 23, Issue 7

July 1990

109 pages

ISSN:0018-9162

Editor:
Bruce D. Shriver
Univ. of Southwestern Louisiana, Lafayette

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Publisher

IEEE Computer Society Press

Washington, DC, United States

Publication History

Published: 01 July 1990

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Cited By

View all

Taher FCallenes-Sloan JSchafer B(2018)A machine learning based hard fault recuperation model for approximate hardware acceleratorsProceedings of the 55th Annual Design Automation Conference10.1145/3195970.3195974(1-6)Online publication date: 24-Jun-2018
https://dl.acm.org/doi/10.1145/3195970.3195974
Takanami IHorita TAkiba MTerauchi MKanno T(2016)A Built-in Self-repair Circuit for Restructuring Mesh-Connected Processor Arrays by Direct Spare ReplacementTransactions on Computational Science XXVII - Volume 957010.1007/978-3-662-50412-3_7(97-119)Online publication date: 1-Feb-2016
https://dl.acm.org/doi/10.1007/978-3-662-50412-3_7
Agarwal ACong JTagiku B(2013)The survivability of design-specific spare placement in FPGA architectures with high defect ratesACM Transactions on Design Automation of Electronic Systems10.1145/2442087.244210418:2(1-22)Online publication date: 11-Apr-2013
https://dl.acm.org/doi/10.1145/2442087.2442104
Henry MNazhandali L(2011)Hybrid super/subthreshold design of a low power scalable-throughput FFT architectureTransactions on High-Performance Embedded Architectures and Compilers IV10.5555/2172445.2172456(175-194)Online publication date: 1-Jan-2011
https://dl.acm.org/doi/10.5555/2172445.2172456
Mirza-Aghatabar MBreuer MGupta SDe Micheli GAl-Hashimi BMueller WMacii E(2010)Algorithms to maximize yield and enhance yield/area of pipeline circuitry by insertion of switches and redundant modulesProceedings of the Conference on Design, Automation and Test in Europe10.5555/1870926.1871226(1249-1254)Online publication date: 8-Mar-2010
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Zhang LHan YXu QLi XLi H(2009)On topology reconfiguration for defect-tolerant NoC-based homogeneous manycore systemsIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2008.200210817:9(1173-1186)Online publication date: 1-Sep-2009
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Horita TKatou YTakanami I(2008)An Analysis for Fault-Tolerant 3D Processor Arrays Using 1.5-Track SwitchesIEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences10.1093/ietfec/e91-a.2.623E91-A:2(623-632)Online publication date: 1-Feb-2008
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Jigang WSrikanthan TWang X(2007)Integrated Row and Column Rerouting for Reconfiguration of VLSI Arrays with Four-Port SwitchesIEEE Transactions on Computers10.1109/TC.2007.108556:10(1387-1400)Online publication date: 1-Oct-2007
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Jigang WSrikanthan T(2006)Reconfiguration Algorithms for Power Efficient VLSI Subarrays with Four-Port SwitchesIEEE Transactions on Computers10.1109/TC.2006.4355:3(243-253)Online publication date: 1-Mar-2006
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Abstract

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Cited By

Index Terms

Recommendations

A verification strategy for fault-detection and fault-tolerance circuits

Saboteur-Based Fault Injection for Quantum Circuits Fault Tolerance Assessment

Testable designs for CMOS VLSI circuits

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Access critical reviews of Computing literature here

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