research-article

A Taxonomy of Reconfiguration Techniques for Fault-Tolerant Processor Arrays

Authors:

Mengly Chean,

Jose A. B. FortesAuthors Info & Claims

Computer, Volume 23, Issue 1

Pages 55 - 69

https://doi.org/10.1109/2.48799

Published: 01 January 1990 Publication History

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Abstract

Focuses on the characterization and classification of reconfiguration techniques. The techniques are differentiated according to the type of redundancy (time or hardware), allocation of redundancy (local or global), replacement unit, (processor or a set of processors), switching domain (global or local), and switching implementation (switching element, bus, or network). Typical techniques from four major classes-set switching, processor switching, local redundancy, and time redundancy-are reviewed. The proposed taxonomy can be used as a guide for future research in design and analysis of reconfiguration schemes.

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Index Terms

A Taxonomy of Reconfiguration Techniques for Fault-Tolerant Processor Arrays

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Reviews

Reviewer: Yi-Bing Lin

Chean and Fortes introduce a taxonomy of reconfiguration techniques for fault-tolerant processor arrays and discuss their distinguishing characteristics. They do not exhaustively survey previously proposed reconfiguration schemes. Instead, they review typical techniques selected from some classes and illustrate the main characteristics of different classes of schemes. The authors show the classes of reconfiguration schemes hierarchically in two figures. Following these classification trees, one can easily read through the paper. The many types of schemes determined by the taxonomy are grouped into four major classes: the set-switching class, the processor-switching class, the local-redundancy class, and the time-redundancy class. A scheme in the set-switching class is characterized by its replacement unit. The authors give a general description of this class and focus on a specific scheme proposed by Kuo and Fuchs [1]. In processor-switching schemes, an available cell directly or indirectly replaces a faulty cell. This class comprises two approaches. In the first approach, functional cells are systematically collected to form a part of the target array. In the second, faulty cells are replaced by their neighbors in a chain fashion until spare cells are reached. In the local-redundancy class, an array is partitioned or systematically reduced to smaller subarrays, each of which can be reconfigured independently. In the time-redundancy approach, the operational cells are assigned the computations that faulty cells would perform if they were operational. This well-written survey can be a valuable starting point for studying the reconfiguration techniques for fault-tolerant processor arrays.

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Published In

Computer Volume 23, Issue 1

January 1990

103 pages

ISSN:0018-9162

Editor:
Bruce D. Shriver
Univ. of Southwestern Louisiana, Lafayette

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IEEE Computer Society Press

Washington, DC, United States

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Published: 01 January 1990

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