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Error-Control Coding in Computers

Published: 01 July 1990 Publication History

Abstract

In this article, intended for readers with basic knowledge in coding, the codes used in actual systems are surveyed. Error control in high-speed memories is examined, including bit-error-correcting/detecting codes, byte-error-correcting/detecting codes, and codes to detect single-byte errors as well as correct single-bit errors and detect double-bit errors. Tape and disk memory codes for error control in mass memories are discussed. Processor error control and unidirectional error-control codes are covered, including the application of the latter to masking asymmetric line faults.

References

[1]
1. T.R.N. Rao and E. Fujiwara, Error-Control Coding for Computer Systems, Prentice Hall, Englewood Cliffs, N.J., 1989.
[2]
2. N. Jarwala, and D.K. Pradhan, "Cost Analysis of On-Chip Error Control Coding for Fault-Tolerant Computers," Proc. FTCS- 17, Computer Society Press, Los Alamitos, Calif., Order No. 778 (microfiche only), July 1987, pp. 278-283.
[3]
3. K. Matsuzawa and E. Fujiwara, "Masking Asymmetric Line Faults Using Semi-Distance Codes," Proc. FTCS-18, Computer Society Press, Los Alamitos, Calif., Order No. 867 (microfiche only), 1988, pp. 354-359.
[4]
4. M.Y. Hsiao, "A Class of Optimal Minimum Odd-Weight-Column SEC-DED Codes," IBM J. R&D, Vol. 14, July 1970, pp. 395- 401.
[5]
5. E. Fujiwara, "Odd-Weight-Column b-Adjacent Error-Correcting Codes," Trans. Inst. Elect. Comm. Eng., Japan, Vol. E61, 1978, pp. 781-787.
[6]
6. T. Tsuchimoto et al., "A Large Computer System M-780," in Japanese, Nikkei Electronics, 396, June 1986, pp. 179-209.
[7]
7. A.M. Patel, "Adaptive Cross-Parity (AXP) Code for a High-Density Magnetic Tape Subsystem," IBM J. R&D, Vol. 29, Dec. 1985, pp. 546-562.
[8]
8. T. Doi et al., "Cross-Interleave Code for Error Correction of Digital Audio Systems," Proc. 64th AES Convention, Nov. 1979.
[9]
9. D.K. Pradhan and S.M. Reddy, "Error Control Techniques for Logic Processors," IEEE Trans. Computers, Vol. C-21, No. 12, Dec. 1972, pp. 1,331-1,337.
[10]
10. T. Krol, "N,K Concept Fault-Tolerance," IEEE Trans. Computers, Vol. C-35, No. 4, Apr. 1986, pp. 339-349.
[11]
11. D.K. Pradhan, "A New Class of Error-Correcting/Detecting Codes for Fault-Tolerant Computer Applications," IEEE Trans. Computers, Vol. C-29, No. 6, June 1980, pp. 471-481.
[12]
12. D.K. Pradhan, ed., Fault-Tolerant Computing: Theory and Techniques, Prentice Hall, Englewood Cliffs, N.J., 1986.
[13]
13. B. Bose and D.K. Pradhan, "Optimal Unidirectional Error Detecting/Correcting Codes," IEEE Trans. Computers, Vol. C- 31, No. 6, June 1982, pp. 564-568.
[14]
14. J. Bruck and M. Blaum, "Some New EC/ AUED Codes," Proc. FTCS-19, Computer Society Press, Los Alamitos, Calif., Order No. 1959, June 1989, pp. 208-215.
[15]
15. D. Nikolos, N. Gaitanis, and G. Philokyprou, "Systematic t-error Correcting/ All Unidirectional Error Detecting Codes," IEEE Trans. Computers, Vol. C-35, No. 5, May 1986, pp. 394-402.
[16]
16. S. Kundu and S.M. Reddy, "On Symmetric Error Correcting Codes and All Unidirectional Error Detecting Codes," IEEE Trans. Computers, Vol. C-39, No. 6, June 1990.
[17]
Blaum, M., "Systematic Unidirectional Error Detecting Codes," IEEE Trans. Computers, Vol. C-37, No. 4, Apr. 1988, pp. 453-457.
[18]
Blaum, M., and van Tilborg, "On t Error Correcting/All Unidirectional Error Detecting Codes," IEEE Trans. Computers, Vol. 38, No. 11, Nov. 1989, pp. 1493-1501.
[19]
Boinck and van Tilborg, "Constructions and Bounds for Systematic tEC/AUED Codes," submitted to IEEE Trans. on Inf. Theory.
[20]
Bose, B., "Burst Unidirectional Error Detecting Codes," IEEE Trans. Computers, Vol. C-35, No. 4, Apr. 1988, pp. 350-353.
[21]
Bose, B., "On Systematic SEC/MUED Code," Proc. FTCS-11, Computer Society Press, Los Alamitos, Calif., Order No. 350 (microfiche only), June 1981, pp. 265-267.
[22]
Bose, B., "Unidirectional Error Correction/ Detection for VLSI Memory," Digest 11th Int'l Symp. Computer Architecture, Computer Society Press, Los Alamitos, Calif., Order No. 538 (microfiche only), June 1984, pp. 242-244.
[23]
Bose, B., and D.J. Lin, "Systematic Unidirectional Error Detecting Codes," IEEE Trans. Computers, Vol. C-34, No. 11, Nov. 1985, pp. 1,026-1,032.
[24]
Bose, B., and T.R.N. Rao, "Theory of Unidirectional Error Correcting/Detecting Codes," IEEE Trans. Computers, Vol. C-31, No. 6, June 1982, pp. 521-530.
[25]
Bossen, D.C., "b-Adjacent Error Correction," IBM J. R&D, Vol. 14, July 1970, pp. 402-408.
[26]
Bossen, D.C., and M.Y. Hsiao, "A System Solution to the Memory Soft-Error Problem," IBM J. R&D, Vol. 24, May 1980, pp. 390-397.
[27]
Chen, C.L., "Byte-Oriented Error-Correcting Codes for Semiconductor Memory Systems," IEEE Trans. Computers, Vol. C-35, No. 7, July 1986, pp. 646-648.
[28]
Dunning, L.A., "SEC-BED-DED Codes for Error Control in Byte-Organized Memory Systems," IEEE Trans. Computers, Vol. C-34, No. 6, June 1985, pp. 557-562.
[29]
Ikeno, K., and G. Nakamura, "Constant-Weight Codes," in Japanese, Trans. Inst. Elect. Comm. Eng., Japan, Vol. 54-A, July 1971, pp. 410-417.
[30]
Imai, H., ed., Essentials of Error-Control Coding Techniques, Academic Press, 1990.
[31]
Kaneda, S., "A Class of Odd-Weight-Column SEC-DED-SbED Codes for Memory System Applications," IEEE Trans. Computers, Vol. C- 33, No. 8, Aug. 1984, pp. 737-739.
[32]
Kaneda, S., and E. Fujiwara, "Single Byte Error Correcting-Double Byte Error Detecting Codes for Memory Systems," IEEE Trans. Computers, Vol. C-31, No. 7, July 1982, pp. 596-602.
[33]
Lin, D.J., and B. Bose, "The Theory and Design of t-Error Correcting and d(d<t)-Unidirectional Error Detecting Codes," IEEE Trans. Computers , Vol. C-37, No. 4, Apr. 1988, pp. 433-439.
[34]
Pradhan, D.K., and J.J. Stiffler, "Error-Correcting Codes and Self-Checking Circuits," Computer , Vol. 13, No. 3, Mar. 1980, pp. 27-37.
[35]
Sakai, S., et al., "A Defect-Tolerant Technology for an Active-Matrix LCD Integrated with Peripheral Circuits," SID 88 Digest, Society for Information Display, Playa del Rey, Calif., 1988, pp. 400-403.
[36]
Weber, de Vroedt, and Broekee, "Bounds and Constructions for Codes Correcting Unidirectional Errors," IEEE Trans. Inf. Theory, Vol. 35, No. 4, July 1989, pp. 797-810.

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Sajjan G. Shiva

The audience for this survey of codes used in actual systems is readers with a basic knowledge of coding theory. The paper surveys error control in high-speed memories, mass memories, and processors and then reviews unidirectional error-control codes. It covers single- and multiple-bit and byte error detection and correction schemes along with the popular single-error-correction, double-error-detection codes. Error control codes applicable to tapes and discs (optical, compact, and WORM) are described. The authors only present one processor error control technique, but they give a fine introduction to unidirectional codes. They predict that the current trend of reduced cost for error-control coding will result in more applications for these coding schemes and that cost-effective low-level coding techniques may offset the need for massive high-level redundancy. The paper is well written and covers a large body of material. A good understanding of the basics of coding theory is a prerequisite.

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Published In

cover image Computer
Computer  Volume 23, Issue 7
July 1990
109 pages
ISSN:0018-9162
Issue’s Table of Contents

Publisher

IEEE Computer Society Press

Washington, DC, United States

Publication History

Published: 01 July 1990

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