research-article

Concurrent error detection in Reed-Solomon encoders and decoders

Authors:

G. C. Cardarilli,

S. Pontarelli,

M. Re,

A. SalsanoAuthors Info & Claims

IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Volume 15, Issue 7

Pages 842 - 846

https://doi.org/10.1109/TVLSI.2007.899241

Published: 01 July 2007 Publication History

Abstract

Reed-Solomon (RS) codes are widely used to identify and correct errors in transmission and storage systems. When RS codes are used for high reliable systems, the designer should also take into account the occurrence of faults in the encoder and decoder subsystems. In this paper, self-checking RS encoder and decoder architectures are presented. The RS encoder architecture exploits some properties of the arithmetic operations in GF(2^m). These properties are related to the parity of the binary representation of the elements of the Galois Field. In the RS decoder, the implicit redundancy of the received codeword, under suitable assumptions explained in this paper, allows implementing concurrent error detection schemes useful for a wide range of different decoding algorithms with no intervention on the decoder architecture. Moreover, performances in terms of area and delay overhead for the proposed circuits are presented.

References

[1]

{1} R. E. Blahut, Theory and Practice of Error Control Codes. Reading, MA: Addison-Wesley Publishing Company, 1983.

Google Scholar

[2]

{2} A. R. Masoleh and M. A. Hasan, "Low complexity bit parallel architectures for polynomial basis multiplication over GF(2m), computers," IEEE Trans. Comput., vol. 53, no. 8, pp. 945-959, Aug. 2004.

Digital Library

Google Scholar

[3]

{3} J. Gambles, L. Miles, J. Has, W. Smith, and S. Whitaker, "An ultra-low-power, radiation-tolerant reed solomon encoder for space applications," in Proc. IEEE Custom Integr. Circuits Conf., 2003, pp. 631-634.

Google Scholar

[4]

{4} A. R. Masoleh and M. A. Hasan, "Error Detection in Polynomial Basis Multipliers over Binary Extension Fields," in Lecture Notes in Computer Science. New York: Springer-Verlag, 2003, vol. 2523, pp. 515-528.

Crossref

Google Scholar

[5]

{5} S. B. Sarmadi and M. A. Hasan, "Concurrent error detection of polynomial basis multiplication over extension fields using a multiple-bit parity scheme," in Proc. IEEE Int. Symp. Defect Fault Tolerance VLSI Syst., 2005, pp. 102-110.

Crossref

Google Scholar

[6]

{6} G. C. Cardarilli, S. Pontarelli, M. Re, and A. Salsano, "Design of a self checking reed solomon encoder," in Proc. 11th IEEE Int. On-Line Test. Symp. (IOLTS'05), 2005, pp. 201-202.

Crossref

Google Scholar

[7]

{7} G. C. Cardarilli, S. Pontarelli, M. Re, and A. Salsano, "A self checking Reed Solomon encoder: Design and analysis," in Proc. IEEE Int. Symp. Defect Fault Tolerance VLSI Syst., 2005, pp. 111-119.

Digital Library

Google Scholar

[8]

{8} M. Gossel, S. Fenn, and D. Taylor, "On-line error detection for finite field multipliers," in Proc. IEEE Int. Symp. Defect Fault Tolerance VLSI Syst., 1997, pp. 307-311.

Crossref

Google Scholar

[9]

{9} Y.-C. Chuang and C.-W. Wu, "On-line error detection schemes for a systolic finite-field inverter," in Proc. 7th Asian Test Symp., 1998, pp. 301-305.

Crossref

Google Scholar

[10]

{10} I. M. Boyarinov, "Self-checking algorithm of solving the key equation," in Proc. IEEE Int. Symp. Inf. Theory, 1998, p. 292.

Google Scholar

[11]

{11} C. Bolchini, F. Salice and D. Sciuto, "A novel methodology for designing TSC networks based on the parity bit code," in Proc. Eur. Design Test Conf., 1997, pp. 440-444.

Crossref

Google Scholar

[12]

{12} Altera Corp., San Jose, CA, "Altera Reed-Solomon compiler user guide 3.3.3," 2006.

Google Scholar

[13]

{13} Xilinx, San Jose, CA, "Xilinx logicore Reed-Solomon decoder v5.1," 2006.

Google Scholar

[14]

{14} D. Nikolos, "Design techniques for testable embedded error checkers, computers," Computer, vol. 23, no. 7, pp. 84-88, Jul. 1990.

Digital Library

Google Scholar

[15]

{15} P. K. Lala, Fault Tolerant and Fault Testable Hardware Design. Englewood Cliffs, NJ: Prentice-Hall, 1985.

Crossref

Google Scholar

Cited By

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Mahapatro AKhilar PJena SKumar RTuruk ADash M(2011)On distributed self fault diagnosis for wireless multimedia sensor networksProceedings of the 2011 International Conference on Communication, Computing & Security10.1145/1947940.1947962(100-105)Online publication date: 12-Feb-2011
https://dl.acm.org/doi/10.1145/1947940.1947962

Index Terms

Concurrent error detection in Reed-Solomon encoders and decoders
1. Hardware
2. Software and its engineering
  1. Software creation and management
    1. Software development techniques
      1. Error handling and recovery

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Reviews

Reviewer: Hao Wang

Reed-Solomon (RS) error-correcting codes are able to detect and correct errors in transmission and storage systems and are used in a wide variety of commercial applications, such as DVD, worldwide interoperability for microwave access (WiMAX), and Advanced Television Systems Committee (ATSC) standards. Measures and techniques for designing a self-checking RS encoder and decoder, able to detect and correct errors introduced in an encoder or decoder by the RS system, are presented in other publications [1,2]. The main contribution of this paper is a self-checking implementation of the arithmetic structures used in RS encoders, with no modification of the decoder architecture. This property enables the reusability of the design of complex digital systems, which makes it attractive to both academia and industry. Additionally, the authors discuss two main properties of the error-free decoder and the performance of the new system in terms of area and delay overhead. Overall, this is a well-written paper that provides a self-checking RS encoder and decoder with the capability of detecting and correcting concurrent errors. Online Computing Reviews Service

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cover image IEEE Transactions on Very Large Scale Integration (VLSI) Systems

IEEE Transactions on Very Large Scale Integration (VLSI) Systems Volume 15, Issue 7

July 2007

119 pages

ISSN:1063-8210

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IEEE Educational Activities Department

United States

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Published: 01 July 2007

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Mahapatro AKhilar PJena SKumar RTuruk ADash M(2011)On distributed self fault diagnosis for wireless multimedia sensor networksProceedings of the 2011 International Conference on Communication, Computing & Security10.1145/1947940.1947962(100-105)Online publication date: 12-Feb-2011
https://dl.acm.org/doi/10.1145/1947940.1947962

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Recommendations

Soft‐input bit‐flipping decoding of generalised concatenated codes for application in non‐volatile flash memories

Jointly designed architecture-aware LDPC convolutional codes and high-throughput parallel encoders/decoders

Pattern-flipping chase-type decoders with error pattern extracting viterbi algorithm over partial response channels

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