A novel charge recycling design scheme based on adiabatic charge pump
Power consumption has become a critical design criterion for integrated circuits given the growing importance of portable battery-operated devices. A typical CMOS gate driven by power supply (VDD) draws energy equal to CLVDD2 during every cycle of ...
Variations-aware low-power design and block clustering with voltage scaling
We present a new methodology which takes into consideration the effect of within-die (WID) process variations on a low-voltage parallel system. We show that in the presence of process variations one should use a higher supply voltage than would ...
Supply switching with ground collapse: simultaneous control of subthreshold and gate leakage current in nanometer-scale CMOS circuits
Power gating has been widely used to reduce subthreshold leakage. However, the efficiency of power gating degrades very fast with technology scaling, which we demonstrate by experiment. This is due to the gate leakage of circuits specific to power ...
A multilayer data copy test data compression scheme for reducing shifting-in power for multiple scan design
The random-like filling strategy pursuing high compression for today's popular test compression schemes introduces large test power. To achieve high compression in conjunction with reducing test power for multiple-scan-chain designs is even harder and ...
A BIST TPG for low power dissipation and high fault coverage
This paper presents a low hardware overhead test pattern generator (TPG) for scan-based built-in self-test (BIST) that can reduce switching activity in circuits under test (CUTs) during BIST and also achieve very high fault coverage with reasonable ...
Diagnosing at-speed scan BIST circuits using a low speed and low memory tester
Numerous solutions have been proposed to reduce test data volume and test application time during manufacturing testing of digital devices. However, time to market challenge also requires a very efficient debug phase. Error identification in the test ...
SIMD processor-based turbo decoder supporting multiple third-generation wireless standards
A programmable turbo decoder is designed to support multiple third-generation wireless communication standards. We propose a hybrid architecture of hardware and software, which has small size, low power, and high performance like hardware ...
Further exploring the strength of prediction in the factorization of soft-decision Reed-Solomon decoding
Reed-Solomon (RS) codes are among the most widely utilized error-correcting codes in digital communication and storage systems. Among the decoding algorithms of RS codes, the recently developed Koetter-Vardy (KV) soft-decision decoding algorithm can ...
Utilizing reverse short-channel effect for optimal subthreshold circuit design
The impact of the reverse short-channel effect (RSCE) on device current is stronger in the subthreshold region due to reduced drain-induced barrier lowering (DIBL) and the exponential dependency of current on threshold voltage. This paper describes a ...
Microarchitecture configurations and floorplanning co-optimization
Microarchitecture configurations and floorplanning are keys to boost throughput, and they are strongly related. In this paper, we propose a new method to optimize them simultaneously. We first concentrate on floorplanning under given microarchitecture ...
Concurrent error detection in Reed-Solomon encoders and decoders
Reed-Solomon (RS) codes are widely used to identify and correct errors in transmission and storage systems. When RS codes are used for high reliable systems, the designer should also take into account the occurrence of faults in the encoder and decoder ...
A low-power multiplier with the spurious power suppression technique
This paper provides the experience of applying an advanced version of our former spurious power suppression technique (SPST) on multipliers for high-speed and low-power purposes. To filter out the useless switching power, there are two approaches, i.e., ...
