IP reuse methodology has been used extensively in SoC (System on Chip) design. In this reuse methodology, while design and implementation cost is saved, manufacturing cost is not. To further reduce the cost, this reuse concept has been proposed at mask ...

The flip-chip packaging is introduced for modern IC designs with higher integration density and larger I/O counts. It is necessary to consider routing obstacles for modern flip-chip designs, where the obstacles could be regions blocked for signal ...

In today's IC production, the design processes of chips, packages, and boards are typically separate from each other. The lack of information from other domains causes significant design convergence problems and greatly reduces design quality. In this ...

Existing routability-driven placers mostly employ rudimentary and often crude congestion models that fail to account for the complexities in modern designs, e.g., the impact of non-uniform wiring stacks, layer directives, partial and/or complete routing ...

Industry routers are very complex and time consuming, and are becoming more so with the explosion in design rules and design for manufacturability requirements that multiply with each technology node. Global routing is just the first phase of a router ...

Datapath is one of the most important components in high performance circuit designs, such as microprocessors, as it is used to manipulate all data. For better performance, a datapath is usually placed with high regularity and compactness. Although cell ...

This work presents PADE, a new placer with automatic datapath extraction and evaluation. PADE applies novel data learning techniques to train, predict, and evaluate potential datapaths using high-dimensional data such as netlist symmetrical structures, ...

In this paper, we propose two methods used in 3D IC placement that effectively exploit the die-to-die thermal coupling in the stack. First, TSVs are spread on each die to reduce the local power density and vertically aligned across dies simultaneously ...

We propose a flow for routing nets within a standard cell that 1) generates candidate routes for point-to-point segments; 2) finds conflicts (electrical shorts and geometric design rule violations) between candidate routes; and 3) solves a SAT instance ...

Symmetry, topology-matching, and length-matching constraints are three major routing considerations to improve the performance of an analog circuit. Symmetry constraints are specified to route matched nets symmetrically with respect to some common axes. ...

Physical synthesis has emerged as one of the most important tools in design closure, which starts with the logic synthesis step and generates a new optimized netlist and its layout for the final signoff process. As stated in [1], "it is a wrapper around ...

We present advanced data structures and algorithms for fast and high-quality global and detailed routing in modern technologies. Global routing is based on a combinatorial approximation scheme for min-max resource sharing. Detailed routing uses exact ...

If pin density exceeds a certain threshold, pin access becomes a challenge for inter-cell signal routing and increasing the number of metal layers cannot improve routability. CMOS and FinFET layouts may never reach this threshold, but Vertical Slit ...

Moore's law requires the shrinking of physical dimensions of the transistors to roughly half their area every two years. This poses a tremendous challenge on how to print and manufacture these ever-shrinking physical components that make up the ...