research-article

Structure-aware placement for datapath-intensive circuit designs

Authors:

Yao-Wen ChangAuthors Info & Claims

DAC '12: Proceedings of the 49th Annual Design Automation Conference

Pages 762 - 767

https://doi.org/10.1145/2228360.2228498

Published: 03 June 2012 Publication History

Abstract

Datapath is one of the most important components in high performance circuit designs, such as microprocessors, as it is used to manipulate all data. For better performance, a datapath is usually placed with high regularity and compactness. Although cell placement has been studied extensively, not much work addresses the optimization of datapaths which are often treated as big macros. In this paper, we propose a structure-aware placement algorithm that can exploit the regular structures of datapath circuits and meanwhile leverage effective techniques to achieve high quality and scalability. Our algorithm applies a nonlinear optimization for wirelength minimization and a sigmoid based density model for density control in datapath circuits. Compared with state-of-the-art works, our algorithm can achieve the best structure-aware placement results efficiently.

References

[1]

coalesCgrip: A Tool for Routing Congestion Analysis. http://homepages.cae.wisc.edu/~adavoodi/gr/cgrip.htm.

[2]

ISPD 2006 Placement Contest. http://www.sigda.org/ispd2006/contest.html.

[3]

Structured Placement Benchmark Suite. http://www.cerc.utexas.edu/utda/download/DP/.

[4]

S. R. Arikati and R. Varadarajan. A signature based approach to regularity extraction. In Proc. of ICCAD, pages 542--545, 1997.

Digital Library

[5]

H. Cai, S. Note, and H. D. Man. A data path layout assembler for high performance dsp circuits. In Proc. of DAC, pages 306--311, 1990.

Digital Library

[6]

T. Chan, A. Chowdhary, B. Krishna, A. Levin, G. Meeker, and N. Sehgal. Challenges of cad development for datapath design. In Intel Technology Journal, Q1, 1999.

[7]

T. Chan, J. Cong, J. Shinnerl, K. Sze, and M. Xie. mPL6: Enhanced multilevel mixed-size placement. In Proc. of DAC, pages 212--214, 2006.

Digital Library

[8]

T.-C. Chen, Z.-W. Jiang, T.-C. Hsu, H.-C. Chen, and Y.-W. Chang. NTUplace3: An analytical placer for large-scale mixed-size designs with preplaced blocks and density constraints. IEEE Trans. on CAD, 27(7):1228--1240, 2008.

Digital Library

[9]

M. R. Corazao, M. A. Khalaf, L. M. Guerra, M. Potkonjak, and J. M. Rabaey. Performance optimization using template mapping for datapath-intensive high-level synthesis. IEEE Trans. on CAD, 5(8):877--888, 1996.

Digital Library

[10]

D. Hill. US patent 6,370,673: Method and system for high speed detailed placement of cells within an integrated circuit design. 2002.

[11]

M. Hirsch and D. Siewiorek. Automatically extracting structure from a logical design. In Proc. of ICCAD, pages 456--459, 1988.

[12]

M.-K. Hsu, Y.-W. Chang, and V. Balabanov. TSV-aware analytical placement for 3D IC designs. In Proc. of DAC, pages 664--669, 2011.

Digital Library

[13]

M.-K. Hsu, S. Chou, T.-H. Lin, and Y.-W. Chang. Routability-driven analytical placement for mixed-size circuit designs. In Proc. of ICCAD, pages 80--84, 2011.

Digital Library

[14]

A. B. Kahng and Q. Wang. Implementation and extensibility of an analytic placer. IEEE Trans. on CAD, 24(5):734--747, 2005.

Digital Library

[15]

J. Kim and S. M. Kang. A timing-driven data path layout synthesis with integer programming. In Proc. of ICCAD, pages 716--719, 1995.

Digital Library

[16]

T. Kutzschebauch and L. Stok. Regularity driven logic synthesis. In Proc. of ICCAD, pages 439--446, 2000.

Digital Library

[17]

W. K. Luk and A. A. Dean. Multi-stack optimization for datapath chip (microprocessor) layout. In Proc. of DAC, pages 110--115, 1989.

Digital Library

[18]

M. Munch, N. When, and M. Glesner. Optimum simultaneous placement and binding for bit-slice architectures. In Proc. of ASPDAC, pages 735--740, 1995.

[19]

H. Nakao, O. Kitada, M. Hayashikoshi, K. Okazaki, and Y. Tsujihashi. A high density datapath layout generation method under path delay constraints. In Proc. of CICC, pages 9.5.1--9.5.5, 1993.

[20]

G.-J. Nam. ISPD 2006 placement contest: Benchmark suite and results. In Proc. of ISPD, pages 167--167, 2006.

Digital Library

[21]

W. C. Naylor, R. Donelly, and L. Sha. US patent 6,301,693: Non-linear optimization system and method for wire length and delay optimization for an automatic electric circuit placer. 2001.

[22]

R. X. Nijssen and J. A. Jess. Two-dimensional datapath regularity extraction. In Proc. of IFIP, pages 110--117, 1996.

[23]

G. Odawara, T. Hiraide, and O. Nishina. Partitioning and placement technique for CMOS gate arrays. IEEE Trans. on CAD, 6(3):355--363, 1987.

Digital Library

[24]

J. Roy, D. Papa, A. Ng, and I. Markov. Satisfying whitespace requirements in top-down placement. In Proc. of ISPD, pages 206--208, 2006.

Digital Library

[25]

P. Spindler, U. Schlichtmann, and F. M. Johannes. Abacus: Fast legalization of standard cell circuits with minimal movement. In Proc. of ISPD, pages 47--53, 2008.

Digital Library

[26]

N. Viswanathan, M. Pan, and C. Chu. Fastplace 3.0: A fast multilevel quadratic placement algorithm with placement congestion control. In Proc. of ASPDAC, pages 135--140, 2007.

Digital Library

[27]

S. Ward, D. A. Papa, Z. Li, C. Sze, C. Alpert, and E. Swartzlander. Quantifying academic placer performance on custom designs. In Proc. of ISPD, pages 91--98, 2011.

Digital Library

[28]

T. T. Ye and G. D. Micheli. Data path placement with regularity. In Proc. of ICCAD, pages 264--271, 2000.

Digital Library

[29]

J.-S. Yim and C.-M. Kyung. Datapath layout optimization using genetic algorithm and simulated annealing. In Proc. of CDT, pages 135--141, 1998.

Cited By

Qiu YXing YZheng XGao PCai SXiong X(2023)Progress of Placement Optimization for Accelerating VLSI Physical DesignElectronics10.3390/electronics1202033712:2(337)Online publication date: 9-Jan-2023
https://doi.org/10.3390/electronics12020337
Pudi DHarrison SStathis DBoppu SHemani ACenkeramaddi L(2022)Methodology for Structured Data-Path Implementation in VLSI Physical Design: A Case StudyElectronics10.3390/electronics1118296511:18(2965)Online publication date: 19-Sep-2022
https://doi.org/10.3390/electronics11182965
Purkayastha SMukherjee S(2022)PHetDP: A Placement Algorithm for Heterogeneous FPGAs with Delayed PackingCircuits, Systems, and Signal Processing10.1007/s00034-022-02159-442:2(801-827)Online publication date: 4-Sep-2022
https://doi.org/10.1007/s00034-022-02159-4
Show More Cited By

Index Terms

Structure-aware placement for datapath-intensive circuit designs
1. Hardware
  1. Electronic design automation
    1. Physical design (EDA)
      1. Placement
      2. Wire routing

Recommendations

Graph-Based Logic Bit Slicing for Datapath-Aware Placement
DAC '17: Proceedings of the 54th Annual Design Automation Conference 2017

Extracting similar datapath bit slices which handle highly parallel bit operations can help a modern placer to obtain better solutions for datapath-oriented designs. A current state-of-the-art datapath bit slicing method achieves the best extraction ...
Routability-driven placement for hierarchical mixed-size circuit designs
DAC '13: Proceedings of the 50th Annual Design Automation Conference

A wirelength-driven placer without considering routability could introduce irresolvable routing-congested placements. Therefore, it is desirable to develop an effective routability-driven placer for modern mixed-size designs employing hierarchical ...
TSV-aware analytical placement for 3D IC designs
DAC '11: Proceedings of the 48th Design Automation Conference

Through-silicon vias (TSVs) are required for transmitting signals among different dies for the three-dimensional integrated circuit (3D IC) technology. The significant silicon areas occupied by TSVs bring critical challenges for 3D IC placement. Unlike ...

Comments

Information & Contributors

Information

Published In

cover image ACM Conferences

DAC '12: Proceedings of the 49th Annual Design Automation Conference

June 2012

1357 pages

ISBN:9781450311991

DOI:10.1145/2228360

General Chair:
Patrick Groeneveld
Magma Design Automation, Inc., San Jose, CA
,
Program Chairs:
Donatella Sciuto
Politecnico di Milano, Milano, Italy
,
Soha Hassoun
Tufts Univ., Medford, MA

Copyright © 2012 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

Sponsors

EDAC: Electronic Design Automation Consortium
SIGDA: ACM Special Interest Group on Design Automation
IEEE-CEDA

In-Cooperation

SIGBED: ACM Special Interest Group on Embedded Systems

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 03 June 2012

Permissions

Request permissions for this article.

Request Permissions

Check for updates

Author Tags

Qualifiers

Research-article

Funding Sources

National Science Council Taiwan

Conference

DAC '12

Sponsor:

EDAC
SIGDA

DAC '12: The 49th Annual Design Automation Conference 2012

June 3 - 7, 2012

California, San Francisco

Acceptance Rates

Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

Upcoming Conference

DAC '25

Sponsor:
sigda

62nd ACM/IEEE Design Automation Conference

June 22 - 26, 2025

San Francisco , CA , USA

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

31
Total Citations
View Citations
534
Total Downloads

Downloads (Last 12 months)39
Downloads (Last 6 weeks)7

Reflects downloads up to 28 Dec 2024

Other Metrics

View Author Metrics

Citations

Cited By

Qiu YXing YZheng XGao PCai SXiong X(2023)Progress of Placement Optimization for Accelerating VLSI Physical DesignElectronics10.3390/electronics1202033712:2(337)Online publication date: 9-Jan-2023
https://doi.org/10.3390/electronics12020337
Pudi DHarrison SStathis DBoppu SHemani ACenkeramaddi L(2022)Methodology for Structured Data-Path Implementation in VLSI Physical Design: A Case StudyElectronics10.3390/electronics1118296511:18(2965)Online publication date: 19-Sep-2022
https://doi.org/10.3390/electronics11182965
Purkayastha SMukherjee S(2022)PHetDP: A Placement Algorithm for Heterogeneous FPGAs with Delayed PackingCircuits, Systems, and Signal Processing10.1007/s00034-022-02159-442:2(801-827)Online publication date: 4-Sep-2022
https://doi.org/10.1007/s00034-022-02159-4
Lin JDeng YYang YChen JLu P(2021)Dataflow-Aware Macro Placement Based on Simulated Evolution Algorithm for Mixed-Size DesignsIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2021.305792129:5(973-984)Online publication date: May-2021
https://doi.org/10.1109/TVLSI.2021.3057921
Lin JHuang WChen YWang YWang P(2021)DAPA: A Dataflow-Aware Analytical Placement Algorithm for Modern Mixed-Size Circuit Designs2021 IEEE/ACM International Conference On Computer Aided Design (ICCAD)10.1109/ICCAD51958.2021.9643441(1-8)Online publication date: 1-Nov-2021
https://doi.org/10.1109/ICCAD51958.2021.9643441
Chou YHsu JChang YChen T(2021)VLSI Structure-aware Placement for Convolutional Neural Network Accelerator Units2021 58th ACM/IEEE Design Automation Conference (DAC)10.1109/DAC18074.2021.9586294(1117-1122)Online publication date: 5-Dec-2021
https://doi.org/10.1109/DAC18074.2021.9586294
Hamolia VMelnyk V(2021)A Survey of Machine Learning Methods and Applications in Electronic Design Automation2021 11th International Conference on Advanced Computer Information Technologies (ACIT)10.1109/ACIT52158.2021.9548117(757-760)Online publication date: 15-Sep-2021
https://doi.org/10.1109/ACIT52158.2021.9548117
Lin JDeng YLi SYu BChang LPeng T(2019)Regularity-Aware Routability-Driven Macro Placement Methodology for Mixed-Size Circuits With ObstaclesIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2018.286783327:1(57-68)Online publication date: Jan-2019
https://doi.org/10.1109/TVLSI.2018.2867833
Wang YYeo DShin H(2019)Effective datapath logic extraction techniques using connection vectorsIET Circuits, Devices & Systems10.1049/iet-cds.2018.508313:6(741-747)Online publication date: 31-Jul-2019
https://doi.org/10.1049/iet-cds.2018.5083
Lin YPan D(2019)Machine Learning in Physical Verification, Mask Synthesis, and Physical DesignMachine Learning in VLSI Computer-Aided Design10.1007/978-3-030-04666-8_4(95-115)Online publication date: 16-Mar-2019
https://doi.org/10.1007/978-3-030-04666-8_4
Show More Cited By

View Options

Login options

Check if you have access through your login credentials or your institution to get full access on this article.

Full Access

Get this Publication

View options

PDF

View or Download as a PDF file.

eReader

View online with eReader.

Media

Figures

Other

Tables

View Table of Contents