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October 2022
High Reliability Soft Error Hardened Latch Designfor Nanoscale CMOS Technology using PVT Variation
- T. Dhanushya,
- T. Latha
Wireless Personal Communications: An International Journal (WPCO), Volume 128, Issue 2Pages 1471–1487https://doi.org/10.1007/s11277-022-10033-4
Abstract
In this paper, a soft error hardened circuit with the aim ofavoiding and detecting-correctingthe soft error strikesat the same timing phase is proposed for high-speed memory applications. The proposed design is completely immune to multiple soft ...
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