In part-I, a novel multi-core node architecture was proposed which when employed in a cluster environment would be capable of tackling computational complexity associated with wide class of applications. Furthermore, it was discussed that by ...

As a result of the increasing requirements of present and future computation intensive applications, there have been many fundamentally divergent approaches such as the Blue-Gene, TRIPS, HERO, Cascade spurred in order to provide increased performance at ...

In this paper the operation of a superscalar processor is studied. An analytical model is developed for computing the throughput and the speedup of the superscalar processors. The throughput is computed as a function of the reoccurrence period of the ...

The NHT-1 I/O (Input/Output) benchmarks are a benchmark suite developed at the Numerical Aerodynamic Simulation Facility (NAS) located at NASA Ames Research Center. These benchmarks are designed to test various aspects of the I/O performance of parallel ...

A standardized view of superscalar architectures is presented, and three current superscalar designs are comparedusing this framework. The designs studied are the Metaflow Light-ning SPARC, the IBM RS/6000, and the Intel i960MM.

A key component in a new high-speed prototype network, called the Multiple Crossbar Network (MCN) being developed at Los Alamos National Laboratory, is a crossbar switching core and its controller. This switching core allows for up to 32 (800 Mbit/...

A multi-user general-purpose parallel system can make good use of the available hardware by sharing it among a mix of jobs with complementary requirements. The central task of the operating system in such an environment is to partition the machine ...

A systematic and economic development of the large-scale computing environment at research centers has to be accompanied by some services providing a survey on the relevant literature. This paper deals with the imbedding of a database on 'High Speed ...

LaZy Superscalar is a processor architecture which delays the execution of fetched instructions until their results are needed by other instructions. This approach eliminates dead instructions and provides the necessary means to fuse dependent ...

We present an architecture designed to transparently and automatically scale the performance of sequential programs as a function of the hardware resources available. The architecture is predicated on a model of computation that views program execution ...

Cloud computing promises flexibility and high performance for users and high cost-efficiency for operators. Nevertheless, most cloud facilities operate at very low utilization, hurting both cost effectiveness and future scalability.

We present Quasar, a ...

Due to the limitations of instruction-level parallelism, thread-level parallelism has become a popular way to improve processor performance. One example is the IBM POWER5TM processor, a two-context simultaneous-multithreaded dual-core chip. In each SMT ...

Dynamic information flow tracking (also known as taint tracking) is an appealing approach to combat various security attacks. However, the performance of applications can severely degrade without hardware support for tracking taints. This paper observes ...

The issue logic of a dynamically-scheduled superscalar processor is a complex mechanism devoted to start the execution of multiple instructions every cycle. Due to its complexity, it is responsible for a significant percentage of the energy consumed by ...

Modern superscalar processors use wide instruction issue widths and out-of-order execution in order to increase instruction-level parallelism (ILP). Because instructions must be committed in order so as to guarantee precise exceptions, increasing ILP ...

Most recent MPP systems employ a fast microprocessor surrounded by a shell of communication and synchronization logic. The CRAY-T3D provides an elaborate shell to support global-memory access, prefetch, atomic operations, barriers, and block transfers. ...

Communication in a parallel system frequently involves moving data from the memory of one node to the memory of another; this is the standard communication model employed in message passing systems. Depending on the application, we observe a variety of ...

Programming models based on messaging continue to be an important programming model for parallel machines. Messaging costs are strongly influenced by a machine's network interface architecture. We examine the impact of architectural support for ...

S-Connect is a new high speed, scalable interconnect system that has been developed to support networks of workstations to efficiently share computing resources. It uses off-the-shelf CMOS technology to directly drive fiber-optic systems at speeds ...