article

Energy-effective issue logic

Authors:

Daniele Folegnani and

Antonio GonzálezAuthors Info & Claims

ACM SIGARCH Computer Architecture News, Volume 29, Issue 2

Pages 230 - 239

https://doi.org/10.1145/384285.379266

Published: 01 May 2001 Publication History

Abstract

The issue logic of a dynamically-scheduled superscalar processor is a complex mechanism devoted to start the execution of multiple instructions every cycle. Due to its complexity, it is responsible for a significant percentage of the energy consumed by a microprocessor. The energy consumption of the issue logic depends on several architectural parameters, the instruction issue queue size being one of the most important. In this paper we present a technique to reduce the energy consumption of the issue logic of a high-performance superscalar processor. The proposed technique is based on the observation that the conventional issue logic wastes a significant amount of energy for useless activity. In particular, the wake-up of empty entries and operands that are ready represents an important source of energy waste. Besides, we propose a mechanism to dynamically reduce the effective size of the instruction queue. We show that on average the effective instruction queue size can be reduced by a factor of 26% with minimal impact on performance. This reduction together with the energy saved for empty and ready entries result in about 90.7% reduction in the energy consumed by the wake-up logic, which represents 14.9% of the total energy of the assumed processor.

References

[1]

G. Albera, I. Bahar, S. Manne "Power and Performance trade-offs using various caching strategies" Proceedings of the Int'l Symposium on low-Power Electronics and Design, 1998

Digital Library

[2]

D. Albonesi "Dynamic IPC/Clock Rate Optimization" Proceedings of the 25th Int'l Symposium on computer Architecture, 1998

Digital Library

[3]

D. Albonesi "The inherent Energy Efficiency of Complexity-Adaptive Processors" Power Driven Microarchitecture Workshop in conjuction with 1SCA-25, 1998

[4]

D. Burger, T. Austin "The SimpleScalar Tool Set", Version 3.0 Technical Report, University of Wisconsin, Madison 1999

[5]

D. Brooks, M. Martonosi "Adaptive Thermal Management for High-Performance Microprocessors", Workshop on Complexity Effective Design in conjuction with ISCA-27, 2000

[6]

D. Brooks, V. Tiwari, M. Martonosi "Wattch: A Framework for Architectural-Level Power Analysis and Optimizations", Proc of the 27th htt'l Symp. on Computer Architecture, 2000

Digital Library

[7]

G. Cai "Architectural Level Power/Performance Optimization and Dynamic Power Estimation", Proc. of the CoolChips tutorial, An Industrial Perspective on Low Power Processor Design in conjunction with MICRO-32, 1999

[8]

R. Canal, A. Gonzzilez and J. Smith "Very Low Power Pipelines using Significance Compression" Proc. of 33rd. Int. Symposium on Microarchitecture (MICRO-33), Monterey. CA (USA), December 10-13. 2000

Digital Library

[9]

T. M. Conte, M. Toburen, M. Reilly "Instruction Scheduling for Low power dissipation in High Performance Microprocessors", Workshop on Power Driven Microarchitecture in conjuction with 1SCA-25,1998

[10]

Intel Corporation "The Intel Architecture Software Developers Manual", 1999

[11]

Intel Corporation "Intel StrongArm SA- 110 Microprocessor Datasheet", 1999

[12]

Mentor Graphics Corporation "QuickPower', 1999

[13]

Synopsys Corporation "PowerMill Data Sheet". 1999

[14]

Transmeta Corporation "The Technology Behind the Crusoe Processor Whitepaper", 2000

[15]

J. Cortadella,T. Lang, E. Mussoll "Reducing thc encrgy of address and Data Buses with the Working-Zone Encoding Technique and its Effect on Multimedia Applications", Workshop on Power Driven Microarchitecture in conjuction with ISCA-25, 1998

[16]

K. Diefendorf, P. K. Dubey "How Multimedia Workloads Will Change Processor Design", IEEE Computer Journal, 30(9), 1997, pages 43-45

Digital Library

[17]

D. Folegnani and A. Gonzilez,"Reducing Power Consumption of the Issue Logic", Proc. of Workshop on Complexity-Effective Design held in conjunction with ISCA 2000, Vancouver (Canada), June 10, 2000

[18]

R. Gonzailez, M. Horowitz "Energy Dissipation in General Purpose microprocessors", IEEE Journal of Solid State Circuits, 31 (9), 1996, pages 1277-1284

[19]

M. Johnson, W. Mangione-Smith "The filter cache: An energy efficient memory structure" Proceedings of the hTt'l Symposium on Microarchitecture, 1997

Digital Library

[20]

M. Kamble, K. Ghose "Analytical Energy Dissipation Models for low power Caches", Proceedings of int'l Symposium on low power Electronics and Design, 1997

Digital Library

[21]

A. Klauser, D. Grunwald, S.Manne "Pipeline gating: Speculation control for energy reduction", Proceedings of the 25th Int'l Symposium on computer Architecture, 1998

Digital Library

[22]

D. Marculescu, "Profile-Driven Code Execution for Low Power Dissipation" in Proc. of Int. Symp on Low Power Electronics and Design, pp. 253-255, 2000

Digital Library

[23]

S. Palacharla "Complexity effective superscalar processors", PhD Thesis, University of Winsconsin, Madison, 1998

Digital Library

[24]

M. Panich "Reducing Instruction Cache Energy Using Gated Wordlines", MS Thesis, MIT, 1999

[25]

H. Sanchez 'Thermal management system for high performance PowerPC microprocessors", Digest of Technical Papers COMPCON IEEE Computer Socie O, International Conference, 1997

Digital Library

[26]

M Shebanow "SPARC64 5: A High Performance and High Reliability 64-bit SPARC Processor", CSLI Public Event, Stanford University, December 1999

[27]

D. Singh, V. Tiwari "Power Challenges in the lnternet World", Proceedings of the CoolChips tutorial, An Industrial Perspective on Low Power Processor Design, in conjunction with MICRO-32, 1999

[28]

C. Small "Shrinking Devices Put the Squeeze on System Packaging", EDN, 39(4), 1994, pp 41-46

[29]

C. Su, A. Despain "Cache Designs for Energy Efficiency", Proceedings of the 28th Hawaii Int 'l Conference on System Science, 1995

Digital Library

[30]

D. Tennenhouse "Pro-Active Computing", Darpa Technical report, 1999

[31]

The CPU Info Center. http://infopad.eecs.berkeley.edu/ClC

[32]

N. Vijaykrishnan,M. Kandennir, M.J. Irwin. H. Kim,W. Ye "A Unified Energy Estimation Framework with Integrated Hardware-Software Optimizations", Proceedings of the 27th lnt'l Symposium on computer Architecture, 2000

Digital Library

[33]

D. Wall "Limits of Instruction-Level Parallelism", Technical report WRL 93/6, Digital WRL, 1993

[34]

K. Wilcox, S. Manne "Alpha Processors: A History of Power Issues and A Look to the Future", Proceedings of the CooIChips tutorial. An Industrial Perspective on Low Power Processor Design in conjunction MICRO-33, 1999

[35]

V. Zyuban "Inherently Lower-Power High performance Superscalar Architectures", PhD Thesis, University of Notre Dame, 2000

Digital Library

[36]

N. Vijaykrishnan, M. Kandermir, M.J. Irwin, H. Kim and W. Ye "Energy-Driven Hardware-Software Optimizations Using SimplePower" Proc. of the 27th Int'l Symposium on Computer Architecture, pp. 95-106 June 2000

Digital Library

[37]

N. Weste and K. Eshraghian. Principles of CMOS VLSI Desing. Addison Wesley, second ed., 1993

Digital Library

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MATSUDA YSHIOYA RANDO H(2022)Reducing Energy Consumption of Wakeup Logic through Double-Stage Tag ComparisonIEICE Transactions on Information and Systems10.1587/transinf.2021EDP7174E105.D:2(320-332)Online publication date: 1-Feb-2022
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Published In

cover image ACM SIGARCH Computer Architecture News

ACM SIGARCH Computer Architecture News Volume 29, Issue 2

Special Issue: Proceedings of the 28th annual international symposium on Computer architecture (ISCA '01)

May 2001

262 pages

ISSN:0163-5964

DOI:10.1145/384285

Editor:
Per Stenström
Chalmers Univ. of Technology

Issue’s Table of Contents

ISCA '01: Proceedings of the 28th annual international symposium on Computer architecture
June 2001
289 pages
ISBN:0769511627
DOI:10.1145/379240
Chairman:
Per Stenström
Chalmers Univ. of Technology

Copyright © 2001 Authors.

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 01 May 2001

Published in SIGARCH Volume 29, Issue 2

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Cited By

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https://doi.org/10.1587/transinf.2021EDP7174
Soliman WPriya BReddy DAnusha PReddy D(2021)Reconfigurable Microarchitecture-Based PMDC Prototype Development for IoT Edge Computing UtilizationIEEE Sensors Journal10.1109/JSEN.2020.302036221:2(2334-2345)Online publication date: 15-Jan-2021
https://doi.org/10.1109/JSEN.2020.3020362
Criswell KAdegbija T(2019)A Survey of Phase Classification Techniques for Characterizing Variable Application BehaviorIEEE Transactions on Parallel and Distributed Systems10.1109/TPDS.2019.292978131:1(224-236)Online publication date: 17-Dec-2019
https://dl.acm.org/doi/10.1109/TPDS.2019.2929781
Adegbija TRogacs APatel CGordon-Ross A(2018)Microprocessor Optimizations for the Internet of Things: A SurveyIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2017.271778237:1(7-20)Online publication date: Jan-2018
https://doi.org/10.1109/TCAD.2017.2717782
Jha SHeirman WFalcón ATubella JGonzález AEeckhout L(2017)Shared resource aware scheduling on power-constrained tiled many-core processorsJournal of Parallel and Distributed Computing10.1016/j.jpdc.2016.10.001100:C(30-41)Online publication date: 1-Feb-2017
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Adegbija TGordon-Ross A(2016)Phase-Based Dynamic Instruction Window Optimization for Embedded Systems2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)10.1109/ISVLSI.2016.96(397-402)Online publication date: Jul-2016
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Guney IYildiz ABayindir ISerdaroglu KBayik UKucuk G(2015)A Machine Learning Approach for a Scalable, Energy-Efficient Utility-Based Cache PartitioningHigh Performance Computing10.1007/978-3-319-20119-1_29(409-421)Online publication date: 20-Jun-2015
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KORA YYAMAGUCHI KANDO H(2014)MLP-Aware Dynamic Instruction Window Resizing in Superscalar Processors for Adaptively Exploiting Available ParallelismIEICE Transactions on Information and Systems10.1587/transinf.2014EDP7177E97.D:12(3110-3123)Online publication date: 2014
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