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- research-articleDecember 2007
Future generation supercomputers II: a paradigm for cluster architecture
- N. Venkateswaran,
- Deepak Srinivasan,
- Madhavan Manivannan,
- T P Ramnath Sai Sagar,
- Shyamsundar Gopalakrishnan,
- VinothKrishnan Elangovan,
- Arvind M,
- Prem Kumar Ramesh,
- Karthik Ganesan,
- Viswanath Krishnamurthy,
- Sivaramakrishnan
ACM SIGARCH Computer Architecture News (SIGARCH), Volume 35, Issue 5December 2007, Pages 61–70https://doi.org/10.1145/1360464.1360467In part-I, a novel multi-core node architecture was proposed which when employed in a cluster environment would be capable of tackling computational complexity associated with wide class of applications. Furthermore, it was discussed that by ...
- research-articleDecember 2007
Future generation supercomputers I: a paradigm for node architecture
- N. Venkateswaran,
- Deepak Srinivasan,
- Madhavan Manivannan,
- T P Ramnath Sai Sagar,
- Shyamsundar Gopalakrishnan,
- VinothKrishnan Elangovan,
- Karthik Chandrasekar,
- Prem Kumar Ramesh,
- Viswanath Venkatesan,
- Arvindakshan Babu,
- Sudharshan
ACM SIGARCH Computer Architecture News (SIGARCH), Volume 35, Issue 5December 2007, Pages 49–60https://doi.org/10.1145/1360464.1360466As a result of the increasing requirements of present and future computation intensive applications, there have been many fundamentally divergent approaches such as the Blue-Gene, TRIPS, HERO, Cascade spurred in order to provide increased performance at ...
- articleJune 2002
- articleDecember 2001
Energy characterization of embedded real-time operating systems
ACM SIGARCH Computer Architecture News (SIGARCH), Volume 29, Issue 5December 2001, Pages 13–18https://doi.org/10.1145/563647.563652In this paper we propose a methodology to analyze the energy overhead due to the presence of an embedded operating system in a wearable device. Our objective is to determine the key parameters affecting the energy consumption of the RTOS allowing the ...
- articleSeptember 1999
Achieving the best performance on superscalar processors
ACM SIGARCH Computer Architecture News (SIGARCH), Volume 27, Issue 4Sept. 1999, Pages 6–11https://doi.org/10.1145/333554.333556In this paper the operation of a superscalar processor is studied. An analytical model is developed for computing the throughput and the speedup of the superscalar processors. The throughput is computed as a function of the reoccurrence period of the ...
- articleJune 1996
A massively parallel and distributed I/O subsystem
ACM SIGARCH Computer Architecture News (SIGARCH), Volume 24, Issue 3June 1 1996, Pages 1–8https://doi.org/10.1145/381718.381722This paper presents ParFiSys, a parallel and distributed file system developed at the UPM. It provides several types of distributed file systems, which may be accessed using different mapping functions. Grouped management and parallelization are ...
- articleDecember 1993
Implementing the NHT-1 application I/O benchmark
ACM SIGARCH Computer Architecture News (SIGARCH), Volume 21, Issue 5Dec. 1993, Pages 23–30https://doi.org/10.1145/165660.165665The NHT-1 I/O (Input/Output) benchmarks are a benchmark suite developed at the Numerical Aerodynamic Simulation Facility (NAS) located at NASA Ames Research Center. These benchmarks are designed to test various aspects of the I/O performance of parallel ...
- articleJune 1992
A comparison of three current superscalar designs
ACM SIGARCH Computer Architecture News (SIGARCH), Volume 20, Issue 3June 1992, Pages 14–21https://doi.org/10.1145/141868.141870A standardized view of superscalar architectures is presented, and three current superscalar designs are comparedusing this framework. The designs studied are the Metaflow Light-ning SPARC, the IBM RS/6000, and the Intel i960MM.
- articleJuly 1991
Design and evaluation of a distributed asynchronous VLSI crossbar switch controller for a packet switched supercomputer network
ACM SIGARCH Computer Architecture News (SIGARCH), Volume 19, Issue 4June 1991, Pages 69–79https://doi.org/10.1145/122576.122583A key component in a new high-speed prototype network, called the Multiple Crossbar Network (MCN) being developed at Los Alamos National Laboratory, is a crossbar switching core and its controller. This switching core allows for up to 32 (800 Mbit/...
- articleDecember 1990
A subclass of Petri Nets as design abstraction for parallel architectures
ACM SIGARCH Computer Architecture News (SIGARCH), Volume 18, Issue 4Dec. 1990, Pages 67–77https://doi.org/10.1145/121973.121982In spite of their increasing popularity for modeling and performance analysis of parallel systems, Petri nets play only a marginal role in the area of synthesis of asynchronous hardware. It is suggested that a change in the perception of their role will ...
- articleMarch 1990
A model for recentralization of computing: (distributed processing comes home)
ACM SIGARCH Computer Architecture News (SIGARCH), Volume 18, Issue 1March 1990, Page 81https://doi.org/10.1145/379126.379136Distributed systems commonly contain heterogencity at all lcvels of systems structure, differentiated by function (special servers), operating systems and architecture within a single system. On the other hand, large mainframes tend to be more ...
- articleDecember 1989
Architecture for a multi-user general-purpose parllel system
ACM SIGARCH Computer Architecture News (SIGARCH), Volume 17, Issue 6Dec. 1989, Pages 50–56https://doi.org/10.1145/77254.77258A multi-user general-purpose parallel system can make good use of the available hardware by sharing it among a mix of jobs with complementary requirements. The central task of the operating system in such an environment is to partition the machine ...