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- posterSeptember 2016
POSTER: hVISC: A Portable Abstraction for Heterogeneous Parallel Systems
PACT '16: Proceedings of the 2016 International Conference on Parallel Architectures and CompilationSeptember 2016, Pages 443–445https://doi.org/10.1145/2967938.2976039Programming heterogeneous parallel systems can be extremely complex because a single system may include multiple different parallelism models, instruction sets, and memory hierarchies, and different systems use different combinations of these features. ...
- posterSeptember 2016
POSTER: Exploiting Asymmetric Multi-Core Processors with Flexible System Sofware
- Kallia Chronaki,
- Miquel Moretó,
- Marc Casas,
- Alejandro Rico,
- Rosa M. Badia,
- Eduard Ayguadé,
- Jesus Labarta,
- Mateo Valero
PACT '16: Proceedings of the 2016 International Conference on Parallel Architectures and CompilationSeptember 2016, Pages 415–417https://doi.org/10.1145/2967938.2976038Energy efficiency has become the main challenge for high performance computing (HPC). The use of mobile asymmetric multi-core architectures to build future multi-core systems is an approach towards energy savings while keeping high performance. However, ...
- posterSeptember 2016
- posterSeptember 2016
POSTER: Hybrid Data Dependence Analysis for Loop Transformations
PACT '16: Proceedings of the 2016 International Conference on Parallel Architectures and CompilationSeptember 2016, Pages 439–440https://doi.org/10.1145/2967938.2974059Loop optimizations span from vectorization, scalar promotion, loop invariant code motion, software pipelining to loop fusion, skewing, tiling and loop parallelization. These transformations are essential in the quest for automated high-performance code ...
- posterSeptember 2016
POSTER: Collective Dynamic Parallelism for Directive Based GPU Programming Languages and Compilers
PACT '16: Proceedings of the 2016 International Conference on Parallel Architectures and CompilationSeptember 2016, Pages 423–424https://doi.org/10.1145/2967938.2974056Early programs for GPU (Graphics Processing Units) acceleration were based on a flat, bulk parallel programming model, in which programs had to perform a sequence of kernel launches from the host CPU. In the latest releases of these devices, dynamic (or ...
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- posterSeptember 2016
POSTER: Pagoda: A Runtime System to Maximize GPU Utilization in Data Parallel Tasks with Limited Parallelism
PACT '16: Proceedings of the 2016 International Conference on Parallel Architectures and CompilationSeptember 2016, Pages 449–450https://doi.org/10.1145/2967938.2974055Massively multithreaded GPUs achieve high throughput by running thousands of threads in parallel. To fully utilize the hardware, contemporary workloads spawn work to the GPU in bulk by launching large tasks, where each task is a kernel that contains ...
- posterSeptember 2016
POSTER: An Optimization of Dataflow Architectures for Scientific Applications
PACT '16: Proceedings of the 2016 International Conference on Parallel Architectures and CompilationSeptember 2016, Pages 441–442https://doi.org/10.1145/2967938.2974054Dataflow computing is proved to be promising in high-performance computing. However, traditional dataflow architectures are general-purpose and not efficient enough when dealing with typical scientific applications due to low utilization of function ...
- posterSeptember 2016
POSTER: ξ-TAO: A Cache-centric Execution Model and Runtime for Deep Parallel Multicore Topologies
PACT '16: Proceedings of the 2016 International Conference on Parallel Architectures and CompilationSeptember 2016, Pages 429–431https://doi.org/10.1145/2967938.2974052Computational task DAGs are executed on parallel computers by a task scheduling algorithm. Intelligent scheduling is critical for achieving high parallelism, low overheads and reduced communication. A key technique for load balancing task DAGs is work ...
- posterSeptember 2016
POSTER: Efficient Self-Invalidation/Self-Downgrade for Critical Sections with Relaxed Semantics
PACT '16: Proceedings of the 2016 International Conference on Parallel Architectures and CompilationSeptember 2016, Pages 433–434https://doi.org/10.1145/2967938.2974050Cache coherence protocols based on self-invalidation allow simpler hardware implementation compared to traditional write-invalidation protocols, by relying on data-race-free semantics and applying self-invalidation and self-downgrade on synchronization ...
- abstractSeptember 2016
Student Research Poster: Network Controller Emulation on a Sidecore for Unmodified Virtual Machines
PACT '16: Proceedings of the 2016 International Conference on Parallel Architectures and CompilationSeptember 2016, Page 454https://doi.org/10.1145/2967938.2971469Paravirtual I/O devices are known to outperform emulated I/O devices but this performance improvement comes with two major drawbacks: Guest machine owners must install hypervisor-specific device drivers every time they switch hypervisors, and these ...
- abstractSeptember 2016
Student Research Poster: Software Out-of-Order Execution for In-Order Architectures
PACT '16: Proceedings of the 2016 International Conference on Parallel Architectures and CompilationSeptember 2016, Page 458https://doi.org/10.1145/2967938.2971466Processor cores are divided into two categories: fast and power-hungry out-of-order processors, and efficient, but slower in-order processors. To achieve high performance with low-energy budgets, this proposal aims to deliver out-of-order processing by ...
- abstractSeptember 2016
Student Research Poster: A Scalable General Purpose System for Large-Scale Graph Processing
PACT '16: Proceedings of the 2016 International Conference on Parallel Architectures and CompilationSeptember 2016, Page 456https://doi.org/10.1145/2967938.2971465Graph analytics is an important and computationally demanding class of data analytics. It is essential to balance scalability, ease-of-use and high performance in large scale graph analytics. As such, it is necessary to hide the complexity of ...
- research-articleSeptember 2016
A DSL Compiler for Accelerating Image Processing Pipelines on FPGAs
PACT '16: Proceedings of the 2016 International Conference on Parallel Architectures and CompilationSeptember 2016, Pages 327–338https://doi.org/10.1145/2967938.2967969This paper describes an automatic approach to accelerate image processing pipelines using FPGAs. An image processing pipeline can be viewed as a graph of interconnected stages that processes images successively. Each stage typically performs a point-...
- research-articleSeptember 2016
A Static Cut-off for Task Parallel Programs
PACT '16: Proceedings of the 2016 International Conference on Parallel Architectures and CompilationSeptember 2016, Pages 139–150https://doi.org/10.1145/2967938.2967968Task parallel models supporting dynamic and hierarchical parallelism are believed to offer a promising direction to achieving higher performance and programmability. Divide-and-conquer is the most frequently used idiom in task parallel models, which ...
- research-articleSeptember 2016
Resource Conscious Reuse-Driven Tiling for GPUs
- Prashant Singh Rawat,
- Changwan Hong,
- Mahesh Ravishankar,
- Vinod Grover,
- Louis-Noel Pouchet,
- Atanas Rountev,
- P. Sadayappan
PACT '16: Proceedings of the 2016 International Conference on Parallel Architectures and CompilationSeptember 2016, Pages 99–111https://doi.org/10.1145/2967938.2967967Computations involving successive application of 3D stencil operators are widely used in many application domains, such as image processing, computational electromagnetics, seismic processing, and climate modeling. Enhancement of temporal and spatial ...
- research-articleSeptember 2016
Vectorization of Multibyte Floating Point Data Formats
PACT '16: Proceedings of the 2016 International Conference on Parallel Architectures and CompilationSeptember 2016, Pages 363–372https://doi.org/10.1145/2967938.2967966We propose a scheme for reduced-precision representation of floating point data on a continuum between IEEE-754 floating point types. Our scheme enables the use of lower precision formats for a reduction in storage space requirements and data transfer ...
- research-articleSeptember 2016
Rinnegan: Efficient Resource Use in Heterogeneous Architectures
PACT '16: Proceedings of the 2016 International Conference on Parallel Architectures and CompilationSeptember 2016, Pages 373–386https://doi.org/10.1145/2967938.2967964Current processors provide a variety of different processing units to improve performance and power efficiency. For example, ARM's big.LITTLE, AMD's APUs, and Oracle's M7 provide heterogeneous processors, on-die GPUs, and on-die accelerators. However, ...
- research-articleSeptember 2016
Reducing Cache Coherence Traffic with Hierarchical Directory Cache and NUMA-Aware Runtime Scheduling
- Paul Caheny,
- Marc Casas,
- Miquel Moretó,
- Hervé Gloaguen,
- Maxime Saintes,
- Eduard Ayguadé,
- Jesús Labarta,
- Mateo Valero
PACT '16: Proceedings of the 2016 International Conference on Parallel Architectures and CompilationSeptember 2016, Pages 275–286https://doi.org/10.1145/2967938.2967962Cache Coherent NUMA (ccNUMA) architectures are a widespread paradigm due to the benefits they provide for scaling core count and memory capacity. Also, the flat memory address space they offer considerably improves programmability. However, ccNUMA ...
- research-articleSeptember 2016
Power Tuning HPC Jobs on Power-Constrained Systems
PACT '16: Proceedings of the 2016 International Conference on Parallel Architectures and CompilationSeptember 2016, Pages 179–191https://doi.org/10.1145/2967938.2967961As we approach the exascale era, power has become a primary bottleneck. The US Department of Energy has set a power constraint of 20MW on each exascale machine. To be able achieve one exaflop under this constraint, it is necessary that we use power ...
- research-articleSeptember 2016
Online Scalability Characterization of Data-Parallel Programs on Many Cores
PACT '16: Proceedings of the 2016 International Conference on Parallel Architectures and CompilationSeptember 2016, Pages 191–205https://doi.org/10.1145/2967938.2967960We present an accurate online scalability prediction model for data-parallel programs on NUMA many-core systems. Memory contention is considered to be the major limiting factor of program scalability as data parallelism limits the amount of ...