Abstract
The emergence of programmable logic devices as processing platforms for digital signal processing applications poses challenges concerning rapid implementation and high level optimization of algorithms on these platforms. This paper describes Abhainn, a rapid implementation methodology and toolsuite for translating an algorithmic expression of the system to a working implementation on a heterogeneous multiprocessor/field programmable gate array platform, or a standalone system on programmable chip solution. Two particular focuses for Abhainn are the automated but configurable realisation of inter-processor communuication fabrics, and the establishment of novel dedicated hardware component design methodologies allowing algorithm level transformation for system optimization. This paper outlines the approaches employed in both these particular instances.
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References
Madahar, B.K., et al.: How rapid is rapid prototyping? analysis of espadon programme results. EURASIP JASP 2003, 580–593 (2003)
Sriram, S., Bhattacharyya, S.S.: Embedded Multiprocessors. Marcel Dekker, New York (2001)
Mc Allister, J., Woods, R., Walke, R.: Embedded context aware hardware component generation for dataflow system exploration. In: Pimentel, A.D., Vassiliadis, S. (eds.) SAMOS 2004. LNCS, vol. 3133, pp. 254–263. Springer, Heidelberg (2004)
McAllister, J., Woods, R., Walke, R., Reilly, D.: Synthesis and high level optimisation of multidimensional dataflow actor networks on fpga. In: IEEE Workshop on Signal Processing Systems, Texas, USA, pp. 164–169 (2004)
Xilinx: Virtex-2 pro platform fpga handbook (2001)
Lee, E.A., Parks, T.M.: Dataflow process networks. Proc. IEEE 83, 773–799 (1995)
Bhattacharyya, S.S.: Software Synthesis from Dataflow Graphs. Kluwer Academic Publishers, Dordrecht (1996)
Lauwereins, R., Engels, M., Ade, M., Peperstraete, J.A.: Grape-2: A rapid prototyping environment for dsp applications. Computer 28, 35–43 (1995)
Hylands, C., et al.: Overview of the ptolemy project. Technical Memorandum UCB/ERL M03/25, University of California at Berkeley (2003)
Laboratory, C.A.P.: PEACE Users Manual v.1.0b. Seoul National University (2004)
Stefanov, T., Zissulescu, C., Turjan, A., Kienhuis, B., Deprettere, E.: System design using kahn process networks: The compaan/laura approach. In: Design Automation and Test in Europe, Paris, France, vol. 1, pp. 340–345 (2004)
Kahn, G.: The semantics of a simple language for parallel programming. In: Proc. IFIP Congress. North Holland Publishing Company, Amsterdam (1974)
Murthy, P.K., Lee, E.A.: Multidimensional synchronous dataflow. IEEE Trans. Signal Processing 50, 2064–2079 (2002)
Kaplan, D.J., Stevens, R.S.: Processing graph method 2.1 semantics (2002)
Park, C., Jung, J., Ha, S.: Extended synchronous dataflow for efficient dsp system prototyping. Design Automation for Embedded Systems 6, 295–322 (2001)
Bilsen, G., Engels, M., Lauwereins, R., Peperstaete, J.: Cyclo-static dataflow. IEEE Trans. Signal Processing 44, 397–408 (1996)
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McAllister, J., Woods, R., Reilly, D., Fischaber, S., Hasson, R. (2005). Rapid Implementation and Optimisation of DSP Systems on SoPC Heterogeneous Platforms. In: Hämäläinen, T.D., Pimentel, A.D., Takala, J., Vassiliadis, S. (eds) Embedded Computer Systems: Architectures, Modeling, and Simulation. SAMOS 2005. Lecture Notes in Computer Science, vol 3553. Springer, Berlin, Heidelberg. https://doi.org/10.1007/11512622_44
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DOI: https://doi.org/10.1007/11512622_44
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-26969-4
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