Abstract
Large knowledge bases form an important applications area for parallel architectures. The special problems of this domain concern the movement and protection of large amounts of complex data in a hierarchy of storage devices and processing elements, in a manner which is sympathetic to the logical structure of the information. This structure is a reflection of the underlying knowledge representation formalism. An analysis of candidate formalisms leads to the specification of a memory architecture for large knowledge bases. The particular problems of paging are studied, and a scheme for semantic caching is proposed. The design of a fast cache employing highly-parallel pattern-directed searching is described. The performance of this cache in a multi-level memory hierarchy is given.
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© 1987 Springer-Verlag Berlin Heidelberg
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Lavington, S.H., Standring, M., Jiang, Y.J., Wang, C.J., Waite, M.E. (1987). Hardware memory management for large knowledge bases. In: de Bakker, J.W., Nijman, A.J., Treleaven, P.C. (eds) PARLE Parallel Architectures and Languages Europe. PARLE 1987. Lecture Notes in Computer Science, vol 258. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-17943-7_131
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DOI: https://doi.org/10.1007/3-540-17943-7_131
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