Abstract
The paper deals with the problem of Automatic Generation of Test Sequences for digital circuits. Genetic Algorithms have been successfully proposed to solve this industrially critical problem; however, they have some drawbacks, e.g., they are often unable to detect some hard to test faults, and require a careful tuning of the algorithm parameters. In this paper, we describe a new parallel version of an existing GA-based ATPG, which exploits competing sub-populations to overcome these problems. The new approach has been implemented in the PVM environment and has been evaluated on a workstation network using some of the standard benchmark circuits. The results show that it is able to significantly improve the results quality (by testing some critical faults) at the expense of increased CPU time requirements.
This work has been partially supported by European Union through the PCI project #9452 94 204 70 (PETREL).
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© 1996 Springer-Verlag Berlin Heidelberg
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Corno, F., Prinetto, P., Rebaudengo, M., Reorda, M.S. (1996). A parallel genetic algorithm for Automatic Generation of Test Sequences for digital circuits. In: Liddell, H., Colbrook, A., Hertzberger, B., Sloot, P. (eds) High-Performance Computing and Networking. HPCN-Europe 1996. Lecture Notes in Computer Science, vol 1067. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-61142-8_583
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DOI: https://doi.org/10.1007/3-540-61142-8_583
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