Abstract
This work describes generalized structures to design 1-of-M QDI (Quasi Delay-Insensitive) asynchronous adders. Those structures allow to design from simple ripple-carry adders to faster parallel-prefix adders. The proposed method is fully automated and integrated in TAST (TIMA Asynchronous Synthesis Tool) tools suite. This paper also demonstrates that the most widely used dual-rail encoding (binary representation in QDI circuits) is not the best solution for numbers’ representation in asynchronous circuits. In fact, according to the domain of values to be represented increasing the radix leads to parallel-prefix adders with lower area, delay and power consumption. Hence, this work enables the designer to optimize his/her design by choosing the appropriate 1-of-M number representation.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Preview
Unable to display preview. Download preview PDF.
Similar content being viewed by others
References
Udding, J.T.: A formal model for defining and classifying delay-insensitive circuits and systems. Distributed Computing 1, 197–204 (1986)
Stevens, K., et al.: An asynchronous instruction length decoder. IEEE JSSC 36(2), 217–228 (2001)
Coates, W., et al.: FLETzero: an asynchronous switching experiment. In: Proceedings of ASYNC, pp. 173–182 (2001)
Woods, J., Day, P., Furber, S., Garside, J., Paver, N., Temple, S.: AMULET1: an asynchronous ARM microprocessor. IEEE Transaction on Computers 46(4), 385–398 (1997)
Renaudin, M.: Asynchronous circuits and systems: a promising design alternative. Journal of microelectronic engineering 54, 133–149 (2000)
Dinh Duc, A.V., et al.: TAST CAD Tools. In: 2nd Asynchronous Circuit Design Workshop, Munich-Germany (January 28–29, 2002)
Renaudin, M., Vivet, P., Robin, F.: A Design Framework for Asynchronous/Synchronous Circuits Based on CHP to HDL Translation. In: International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC), Barcelona, Spain, April 19– 21, pp. 135–144 (1999)
Martin, A.J.: Synthesis of Asynchronous VLSI Circuits. Internal Report, Caltech-CS_TR- 93–28, California Institute of Technology, Pasadena (1993)
Rigaud, J.-B., Renaudin, M.: Modeling and design/synthesis of arbitration problems. In: AINT 2000, Proceedings of the Asynchronous Interfaces: Tools, Techniques and Implementations Work-shop, TU Delft, The Netherlands, July 19–20, pp. 121–128 (2000)
Rigaud, J.-B., Quartana, J., Fesquet, L., Renaudin, M.: High-Level Modeling and Design of Asynchronous Arbiters for On-Chip Communication Systems. In: Design Automation and Test Conference (DATE), Paris, France (March 4–7, 2002)
Sklansky, J.: Conditional-sum addition logic. IRE Trans. Electronic Computers 9(2), 226–231 (1960)
Brent, R., Kung, H.: A Regular Layout for Parallel Adders. IEEE Transactions on Computers C-31(3), 260–264 (1982)
Kogge, P., Stone, H.: A Parallel Algorithm for the Efficient Solution of General Class of Recurrence Equation. IEEE Trans. on Computers 22(8), 783–791 (1973)
Sparsø, J., Staunstrup, J., Dantzer-Sørensen, M.: Design of delay insensitive circuits using multi-ring structures. In: Proceedings of EURO–DAC, Germany, pp. 15–20 (1992)
David, I., Ginosar, R., Yoeli, M.: An efficient implementation of Boolean functions as selftimed circuits. IEEE Transactions on Computers 41(1), 2–11 (1992)
Kondratyev, A., Lwin, K.: Design of asynchronous circuits using synchronous CAD tools. IEEE Design and Test of Computers 19(4), 107–117 (2002)
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2003 Springer-Verlag Berlin Heidelberg
About this paper
Cite this paper
Fragoso, J.L., Sicard, G., Renaudin, M. (2003). Power/Area Tradeoffs in 1-of-M Parallel-Prefix Asynchronous Adders. In: Chico, J.J., Macii, E. (eds) Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation. PATMOS 2003. Lecture Notes in Computer Science, vol 2799. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-39762-5_19
Download citation
DOI: https://doi.org/10.1007/978-3-540-39762-5_19
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-20074-1
Online ISBN: 978-3-540-39762-5
eBook Packages: Springer Book Archive