Abstract
Energy efficient buffer circuits enable high speed and reliable information transfer among sub-systems of System on Chip (SoC). A novel buffer circuit design exploiting the steep slope characteristics of tunnel FETs (TFET) has been proposed and benchmarked with 20 nm Si FinFET technology. The analysis is performed considering the parameters such as iso-area, iso-energy, iso-speed and noise margins for energy efficiency and reliability. It is clearly evident that TFET buffers exhibit improved speed of operation and high energy efficiency over FinFET buffers for scaled supply voltages, demonstrating suitability for applications such as Internet of things (IoT) SoCs. To further exemplify the buffer circuit performance, TFET/FinFET pass transistor based full adder carry circuit is implemented whose output load is driven by TFET/FinFET buffer. Unlike FinFET buffer circuits, TFET buffers prove to be reliable and energy efficient in driving larger loads despite the area overhead caused due to the unidirectional current conduction of TFETs.
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Acknowledgement
The authors would like to thank the funding support from Department of Science and Technology (DST) SERC young scientist grant NO: SBFTP/ETA-0101/2014.
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Aditya, J., Harshita, V., Vaddi, R. (2017). Exploiting Characteristics of Steep Slope Tunnel Transistors Towards Energy Efficient and Reliable Buffer Designs for IoT SoCs. In: Kaushik, B., Dasgupta, S., Singh, V. (eds) VLSI Design and Test. VDAT 2017. Communications in Computer and Information Science, vol 711. Springer, Singapore. https://doi.org/10.1007/978-981-10-7470-7_26
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DOI: https://doi.org/10.1007/978-981-10-7470-7_26
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